參數(shù)資料
型號(hào)： TEA5766UK
廠商： ST-ERICSSON
元件分類： 接收器
英文描述： FM, AUDIO SINGLE CHIP RECEIVER, PBGA25
封裝： 3.30 X 3.25 MM, 0.60 MM HEIGHT, WLCSP-25
文件頁(yè)數(shù)： 13/60頁(yè)
文件大?。?/td> 298K
代理商： TEA5766UK
TEA5766UK_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 22 March 2007
19 of 59
NXP Semiconductors
TEA5766UK
Stereo FM radio + RDS
If the LSYNCMSK bit is logic 0 and synchronization is lost the TEA5766UK automatically
starts a new synchronization search. It will not generate a hardware interrupt. The host
processor can wait until the RDS decoder is synchronized again; this will be indicated by
the DAVFLG and the SYNC status bit (this requires the DAVMSK being set).
The LSYNCFL is reset by a read of the INTMSK byte 1R.
The LSYNCMSK is not reset by a read of the INTMSK byte; it must be set or reset by the
host processor. Resetting it automatically would change the status of the TEA5766UK and
cause an automatic synchronization search as described above.
How the synchronization is dened is explained in
EN 62106 Specication of the radio
data system (RDS) for VHF/FM sound broadcasting range from 87.5 to 108 MHz, 1998
and in brief in Section 9.
8.2.4 IF frequency: IFFLAG
During automatic frequency search, preset or AF update, the FM part of the TEA5766UK
performs a check on the received IF frequency as a measure of the level of interference in
the channel received. If an incorrect IF frequency is received then this indicates the
presence of strong interferers or tuning to an image and the IFFLAG bit in the INTFLAG
register is set. Also a preset to a channel with no signal will result in a wrong IF count
value and hence setting of the IFFLAG.
When a search, preset or AF update is nished the FRRFLAG will be set to indicate this
and generates an interrupt. The host processor can now read the outcome of the registers
which will contain the IF count value and the IFFLAG status of the channel it is tuned to. In
case of an AF update the IF count value of the alternative frequency will be in the
registers, also when it jumps back because it will then not start a new IF count. Note:
15.6 ms after the tuning algorithm has been completed the IF counter will start a new
count. So 31.25 ms after a failed AF update the IF count result will be equal again to that
of the channel from where the jump was initiated.
15.6 ms after the FRRFLAG has been set the IF counter will start to run continuously on
the tuned frequency and if the conditions for correct frequency are not met then this sets
the IFFLAG bit in the interrupt register. When the IFMSK is set this will also cause an
interrupt.
The IFFLAG bit is cleared by a read of byte 1R, or by starting the tuning algorithm.
8.2.5 RSSI threshold: LEVFLAG
The level voltage reects the eld strength received by the antenna. The level voltage is
analog to digital converted with 4 bits and output via the bus. This 4-bit level value can be
compared to a threshold level set by the SSL bits in Table 16 or the LHSW bit in Table 19.
The level ADC (which converts the analog value to digital) can be triggered to convert in
two ways.
During a tuning step, a search, a preset or an AF update the LEVFLAG is triggered by
these algorithms and compares the level with the threshold set by the SSL bits. The
LEVFLAG bit is set if the RSSI level drops below the threshold level set by the SSL bits in
Table 16 The hardware interrupt is only generated if the corresponding mask bit is set.
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