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參數(shù)資料
| 型號： | TC6387XB |
| 廠商： | Toshiba Corporation |
| 英文描述： | SD Memory Card / SDIO Card Controller |
| 中文描述： | SD卡/ SDIO卡控制器 |
| 文件頁數(shù)： | 51/62頁 |
| 文件大?。?/td> | 1406K |
| 代理商： | TC6387XB |
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TC6387XB Specification
Rev. 1.0 02/02/06
TOTAL
62
PAGE NO.51
TOSHIBA CONFIDENTIAL
(3)
Standard Memory Interface Signal AC Characteristic
(Vcc=3.0-3.6V,Ta=0-70degree C)
Symbol
thos1
Address setup to #HCS
thos2
#HCS, #HBEL, #HBEH setup to #HOE or
#HWE
thos3
Address setup to #HOE or #HWE low
thos4
Address setup to #HOE or #HWE low
tpd0
Data delay time after #HWE low
thoh1
Data hold after #HWE high
thoh2
#HCS, #HBEL, #HBEH hold asserted
after #HOE or #HWE de-asserted
thoh3
Address
Hold
de-asserted
twh1
#HOE high time
twh2
#HWE high time
twl1
#HOE low time
twl2
#HWE low time
tos1
Data Setup for HRDY Release
tpdh1
#HOE,HD[15:0] hold time
t1
#HOE low to HRDY low time
t2
#HWE low to HRDY low time
tw1
HRDY low time
tw2
HRDY low time
*1 There are two ways to have wait modes.
A. External wait mode method(ie. not to use CPU generated wait time):
Please input #HOE/#HWE signal using pulse width of 3HCLK minimum. If this has been applied, HRDY of
TC6380AF signal will be activated and read/write cycle will be extended to access registers. By this method,
read/write access cycle will become 16HCLK maximum.
B. Internal wait mode method(ie. use CPU generated wait time):
Please input #HOE/#HWE signal using enough pulse width, which should be 16HCLK minimum. If this has
been applied, HRDY signal is not necessary for TC6380AF register read/write operations.
Parameter
Min
0
20
Max
-
-
Unit
ns
ns
Notes
20
20
-
5
10
-
-
ns
ns
ns
ns
ns
1HCLK
-
-
after
#HOE
or
#HWE
5
-
ns
3HCLK
3HCLK
3HCLK
3HCLK
1HCLK
5
15
15
1HCLK
1HCLK
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*1
*1
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