參數(shù)資料
型號(hào): TC6387XB
廠商: Toshiba Corporation
英文描述: SD Memory Card / SDIO Card Controller
中文描述: SD卡/ SDIO卡控制器
文件頁(yè)數(shù): 33/62頁(yè)
文件大?。?/td> 1406K
代理商: TC6387XB
TC6387XB Specification
Rev. 1.0 02/02/06
TOTAL
62
PAGE NO.33
TOSHIBA CONFIDENTIAL
4.5.15 End bit error interrupt
+ Interrupt Assert Condition
If a bit that should be the end bit for the response, read data or CRC status received from the card is "0", an
interrupt for detecting an incorrect end bit is generated.
+ Factor Evaluation Method
In the case of SD memory Card, the SEND bit(D2) of SD Buffer Control & Error Status Register(Offset:01E-
01Fh) and the WEBER bit, REBER bit, SEBER bit and CEBER bit(D5-2) of SD Error Detail Status
Register(Offset:02C-02Fh) are set to "1".
In the case of SDIO Card, the SEND bit(D2) of SD Buffer Control & Error Status Register(Offset:11E-11Fh) and
the WEBER bit, REBER bit and CEBER bit(D5-4,2) of SD Error Detail Status Register(Offset:12C-12Fh) are set
to "1".
Bit
5
4
3
2
Name
WEBER
REBER
SEBER
CEBER
Error factor
Notes
End bit error for Write CRC status
End bit error for read data
End bit error of a response for automatically issued CMD12
End bit error for a response (other than SEBER )
Only SD memory Card
+De-asserting Method
SD memory Card
(1) "0" is written into the SEND bit(D2) of SD Buffer Control & Error Status Register(Offset:01E-01Fh).
(2) "1" is written into the MEND bit(D18) of SD Interrupt Mask Register(Offset:020-023h).
(3) Hardware reset by #PCLR = “0”.
(4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:0E0h).
SDIO Card
(1) "0" is written into the SEND bit(D2) of SD Buffer Control & Error Status Register(Offset:11E-11Fh).
(2) "1" is written into the MEND bit(D18) of SD Interrupt Mask Register(Offset:120-123h).
(3) Hardware reset by #PCLR = “0”.
(4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:1E0h).
HCLK
SDCLK
SDCMD
#HINT
End bit
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