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參數(shù)資料
| 型號： | TC6387XB |
| 廠商： | Toshiba Corporation |
| 英文描述： | SD Memory Card / SDIO Card Controller |
| 中文描述： | SD卡/ SDIO卡控制器 |
| 文件頁數(shù)： | 22/62頁 |
| 文件大小： | 1406K |
| 代理商： | TC6387XB |
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TC6387XB Specification
Rev. 1.0 02/02/06
TOTAL
62
PAGE NO.22
TOSHIBA CONFIDENTIAL
+ Factor Evaluation Method
In the case of SD memory Card, the SRWA bit(D2) of SD Card Status Register(Offset:01C-01Dh) is set to "1". In
the case of SDIO Card, the SRWA bit(D2) of SD Card Status Register(Offset:11C-11Dh) is set to "1".
+De-asserting Method
SD memory Card
(1) "0" is written into the SRWA bit(D2) of SD Card Status Register(Offset:01C-01Dh).
(2) "1" is written into the MRWA bit(D2) of SD Interrupt Mask Register(Offset:020-023h).
(3) Hardware reset by #PCLR = “0”.
(4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:0E0h).
SDIO Card
(1) "0" is written into the SRWA bit(D2) of SD Card Status Register(Offset:11C-11Dh)
(2) "1" is written into the MRWA bit(D2) of SD Interrupt Mask Register(Offset:120-123h).
(3) Hardware reset by #PCLR = “0”.
(4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:1E0h).
4.5.7 Illegal access error interrupt
+ Interrupt Assert Condition
When an incorrect command index is written into SD Command Register(Offset:000-001h, 100-101h), an interrupt
is generated. Each of the following cases is recognized as an incorrect index. (3) is only applying to SD memory
Card.
(1) SD Command Register is written before the previously issued command is not completed.
(2) Though the REP2-0 bits(D10-8) are set to 011b(no response), the NTDT bit(D11) is set to 1b(with data).
(3) Though the CMD1-0 bits(D7-6) are set to 00b and the CIX bits(D5-0) are set to 001100b(CMD12), the NTDT
bit(D11) is set to 1b(with data).
#HINT
HCLK
SDCLK
HA[7-0]
#HWE
0x00
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