參數(shù)資料
型號： TAS5028PAGRG4
廠商： Texas Instruments, Inc.
英文描述： 8 Channel Digital Audio PWM Processor
中文描述： 8通道數(shù)字音頻PWM處理器
文件頁數(shù)： 44/84頁
文件大小： 1051K
代理商： TAS5028PAGRG4
Electrical Specifications
36
SLES112 — June 2004
TAS5028
3.4
Electrical Characteristics Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
3.3 V TTL and 5 V
(6)
tolerant
High-level output voltage
1.8-V LVCMOS (XTL_OUT)
3.3-V TTL and 5 V
(6)
tolerant
Low-level output voltage
1.8-V LVCMOS (XTL_OUT)
TEST CONDITIONS
I
OH
= -4 mA
I
OH
= - 0.55 mA
I
OL
= 4 mA
I
OL
= 0.75 mA
MIN
2.4
TYP
MAX
UNITS
V
OH
High level output voltage
V
1.44
V
OL
Low level output voltage
0.5
V
0.5
±
20
±
1
±
1
±
1
±
1
±
1
±
20
I
OZ
High-impedance output current
3.3-V TTL
μ
A
3.3-V TTL
V
I
= V
IL
V
I
= V
IL
V
I
= 0 V DVDD = 3 V
V
I
= V
IH
V
I
= V
IH
V
I
= 5.5 V DVDD = 3 V
Fs = 48 kHz
I
IL
Low-level input current
Low level input current
1.8-V LVCMOS (XTL_IN)
5 V tolerant
(5)
μ
A
3.3-V TTL
I
IH
High-level input current
High level input current
1.8-V LVCMOS (XTL_IN)
5 V tolerant
(5)
μ
A
140
Digital supply voltage DVDD
Digital supply voltage, DVDD
Fs = 96 kHz
150
mA
I
DD
Input supply current
Fs = 192kHz
155
Power down
8
Analog supply voltage AVDD
Analog supply voltage, AVDD
Normal
20
mA
Power down
2
NOTES:
5. 5-V tolerant inputs are SDA, SCL, RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, and SDIN4.
6. 5-V tolerant outputs are SCL and SDA
3.5
PWM Operation at Recommended Operating Conditions Over 0 C to 70 C
PARAMETER
TEST CONDITIONS
32-kHz data rate
±
4%
44.1-, 88.2-, 176.4-kHz data rate
±
4%
48, 96, 192 kHz data rate
±
4%
MODE
VALUE
384
UNITS
kHz
12 x sample rate
Output sample rate 1X – 8 x over sampled
Output sample rate 1X 8 x over sampled
8, 4, and 2 x sample rate
8, 4, and 2 x sample rate
352.8
384
kHz
kHz
3.6
Switching Characteristics
3.6.1 Clock Signals Over Recommended Operating Conditions (Unless Otherwise
Noted)
3.6.1.1
PLL Input Parameters and External Filter Components
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
f
XTALI
f
MCLKI
Frequency, XTAL IN
Only use 13.5-MHz crystal
≤
1000 ppm
13.5
MHz
Frequency, MCLK (1 / t
cyc2
)
MCLK duty cycle duty cycle
2
50
MHz
40%
50%
60%
MCLK minimum high time
≥
2-V MCLK = 49.152 MHz, Within the min
and max duty cycle constraints
5
ns
MCLK minimum low time
≤
0.8-V MCLK = 49.152 MHz,
Within the min and max duty cycle constraints
5
ns
LRCLK allowable drift before LRCLK reset
10
MCLKs
External PLL filter cap C1
SMD 0603 Y5V
100
nF
External PLL filter cap C2
SMD 0603 Y5V
10
nF
nF
External PLL filter resistor R
SMD 0603, metal film
200
External VRA_PLL decoupling
SMD, Y5V
100
See the TAS5028
Example Application Schematic
section.
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