參數(shù)資料
型號： TAS5028PAGRG4
廠商： Texas Instruments, Inc.
英文描述： 8 Channel Digital Audio PWM Processor
中文描述： 8通道數(shù)字音頻PWM處理器
文件頁數(shù)： 20/84頁
文件大小： 1051K
代理商： TAS5028PAGRG4
Introduction
12
SLES112 — June 2004
TAS5028
DAP7
Volume
(0xD7)
DAP8
Volume
(0xD8)
Master Vol
(0xD9)
A
B
C
D
E
F
G
H
G
H
A
B
C
D
E
F
A
B
C
D
E
F
G
H
G
H
A
B
C
D
E
F
A
B
C
E
F
G
H
G
H
A
B
C
D
E
F
A
B
C
D
E
F
G
H
G
H
IP Mixer 1
(I2C 0x41)
A
B
C
D
E
F
A
B
C
D
E
F
G
H
G
H
A
B
C
D
E
F
A
B
C
D
E
F
G
H
G
H
A
B
C
D
E
F
A
B
C
D
E
F
G
H
G
H
A
B
C
D
E
F
A
B
C
D
E
F
G
H
G
H
A
B
C
D
E
F
IP Mixer 2
(I2C 0x42)
IP Mixer 3
(I2C 0x43)
IP Mixer 4
(I2C 0x44)
IP Mixer 5
(I2C 0x45)
IP Mixer 6
(I2C 0x46)
IP Mixer 7
(I2C 0x47)
IP Mixer 8
(I2C 0x48)
Bass &
Treble 1
(0xDA-
0xDD)
L to
PWM1
OP Mixer 1
(I2C 0xAA)
8X2 Output
Mixer
Bass &
Treble 1
(0xDA-
0xDD)
R to
PWM2
OP Mixer 2
(I2C 0xAB)
8X2 Output
Mixer
Bass &
Treble 2
(0xDA-
0xDD)
LS to
PWM3
OP Mixer 3
(I2C 0xAC)
8X2 Output
Mixer
Bass &
Treble 2
(0xDA-
0xDD)
RS to
PWM4
OP Mixer 4
(I2C 0xAD)
8X2 Output
Mixer
Bass &
Treble 3
(0xDA-
0xDD)
LBS to
PWM5
OP Mixer 5
(I2C 0xAE)
8X2 Output
Mixer
Bass &
Treble 3
(0xDA-
0xDD)
RBS to
PWM6
OP Mixer 6
(I2C 0xAF)
8X2 Output
Mixer
Bass &
Treble 1
(0xDA-
0xDD)
C to
PWM7
OP Mixer 7
(I2C 0xB0)
8X3 Output
Mixer
Bass &
Treble 4
(0xDA-
0xDD)
Sub to
PWM8
OP Mixer 8
(I2C 0xB1)
8X3 Output
Mixer
DAP1
Volume
(0xD1)
Master Vol
(0xD9)
DAP2
Volume
(0xD2)
Master Vol
(0xD9)
DAP3
Volume
(0xD3)
Master Vol
(0xD9)
DAP4
Volume
(0xD4)
Master Vol
(0xD9)
DAP5
Volume
(0xD5)
Master Vol
(0xD9)
DAP6
Volume
(0xD6)
Master Vol
(0xD9)
Master Vol
(0xD9)
SDIN1-L(L)
SDIN1-R (R)
SDIN2-L (LS)
SDIN2-R (RS)
SDIN3-L (LBS)
SDIN3-R (RBS)
SDIN4-L (C)
SDIN4-R (LFE)
SDIN1-L(L)
SDIN1-R(R)
SDIN2-L (LS)
SDIN2-R (RS)
SDIN3-L (LBS)
SDIN3-R (RBS)
SDIN4-L (C)
SDIN4-R (LFE)
SDIN1-L(L)
SDIN1-R(R)
SDIN2-L(LS)
SDIN2-R (RS)
SDIN3-L (LBS)
SDIN3-R (RBS)
SDIN4-L (C)
SDIN4-R (LFE)
SDIN1-L(L)
SDIN1-R(R)
SDIN2-L(LS)
SDIN2-R(RS)
SDIN3-L (LBS)
SDIN3-R (RBS)
SDIN4-L (C)
SDIN4-R (LFE)
SDIN1-L(L)
SDIN1-R(R)
SDIN2-L(LS)
SDIN2-R (RS)
SDIN3-L(LBS)
SDIN3-R (RBS)
SDIN4-L (C)
SDIN4-R (LFE)
SDIN1-L(L)
SDIN1-R(R)
SDIN2-L(LS)
SDIN2-R (RS)
SDIN3-L (LBS)
SDIN3-R(RBS)
SDIN4-L (C)
SDIN4-R (LFE)
SDIN1-L(L)
SDIN1-R(R)
SDIN2-L(LS)
SDIN2-R (RS)
SDIN3-L (LBS)
SDIN3-R(RBS)
SDIN4-L(C)
SDIN4-R (LFE)
SDIN1-L(L)
SDIN1-R(R)
SDIN2-L(LS)
SDIN2-R (RS)
SDIN3-L (LBS)
SDIN3-R(RBS)
SDIN4-L (C)
SDIN4-R(LFE)
Default Input Is
BOLD
Figure 1-4. TAS5028 DAP Architecture With I
2
C Registers (Fs
≤
96 kHz)
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