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Introduction
9
SLES112 — June 2004
TAS5028
1.4.2.1
Serial Audio Interface
The TAS5028 operates as a slave only / receive only serial data interface in all modes. The TAS5028 has four
PCM serial data interfaces to permit eight channels of digital data to be received though the SDIN1, SDIN2,
SDIN3, and SDIN4 inputs. The serial audio data is in MSB first, two’s complement format.
The serial data input interface of the TAS5028 can be configured in right justified, I
2
S, or left-justified modes.
The serial data interface format is specified using the I
2
C data interface control register. The supported formats
and word lengths are shown in Table 1-1.
Table 1-1. Serial Data Formats
RECEIVE SERIAL DATA
INTERFACE FORMAT
WORD LENGTHS
Right justified
16
Right justified
20
Right justified
24
I2S
16
I2S
20
I2S
24
Left Justified
16
Left Justified
20
Left Justified
24
Serial data is input on SDIN1, SDIN2, SDIN3, and SDIN4. The TAS5028 accepts 32-, 38-, 44.1-, 48-, 88.2-,
96-, 176.4-, and 192-kHz serial data in 16-, 20-, or 24-bit data in left, right, and I
2
S serial data formats using
a 64-Fs SCLK clock and a 128, 192, 256, 384, 512, or 768 x Fs MCLK rates (up to a maximum of 50 MHz).
The parameters of this clock and serial data interface are I
2
C configurable.
1.4.3 I
2
C Serial Control Interface
The TAS5028 has an I
2
C serial control slave interface (address 0x36) to receive commands from a system
controller. The serial control interface supports both normal-speed (100 kHz) and high-speed (400 kHz)
operations without wait states. Since the TAS5028 has a crystal time base, this interface operates even when
MCLK is absent.
The serial control interface supports both single byte and multi-byte read / write operations for status registers
and the general control registers associated with the PWM. However, for the DAP data processing registers,
the serial control interface also supports multiple byte (4 byte) write operations.
The I
2
C supports a special mode which permits I
2
C write operations to be broken up into multiple data write
operations that are multiples of 4 data bytes. These are 6 byte, 10 byte, 14 byte, 18 byte ... etc write operations
that are composed of a device address, read/write bit, and subaddress and any multiple of 4 bytes of data.
This permits the system to incrementally write large register values without blocking other I
2
C transactions.
In order to use this feature, the first chunk of data is written to the target I
2
C address and each chunk of
subsequent data is written to a special append register (0xFE), until all the data is written and a stop bit is sent.
An incremental read operation is not supported.
1.4.4 Device Control
The TAS5028 control section provides the control and sequencing for the TAS5028. The device control
provides both high and low level control for the serial control interface, clock and serial data interfaces, digital
audio processor, and pulse width modulator sections.
1.4.5 Digital Audio Processor (DAP)
The DAP arithmetic unit is used to implement all audio processing functions – soft volume, bass and treble
processing, and input and output mixing. Figure 1-6 shows the TAS5028 DAP architecture.