參數(shù)資料
型號: SYM53C140
廠商: LSI CORP
元件分類: 其它接口
英文描述: Ultra2 SCSI Bus Expander(Ultra2 SCSI總線擴(kuò)展器)
中文描述: SPECIALTY INTERFACE CIRCUIT, PQFP160
封裝: 32 MM, PLASTIC, QFP-160
文件頁數(shù): 25/68頁
文件大?。?/td> 928K
代理商: SYM53C140
Interface Signal Descriptions
2-11
become the HVD driver/receiver direction control signals. The A and B
Sides are independently controlled.
When the single-ended mode is selected by the lack of HVD_MODE and
the correct DIFFSENS voltage, the plus signal leads are internally tied to
ground and the minus SCSI signals become the single-ended
input/outputs.
When the Low-Voltage Differential mode is selected by the lack of
HVD_MODE and the correct DIFFSENS voltage, the plus and minus
signal leads are differential signal pairs.
2.1.7.9 Clock (CLOCK)
This is the 40 MHz oscillator input to the SYM53C140. It is the clock
source for the protocol control state machines and timing generation
logic. This clock is not used in any bus signal transfer paths.
2.1.7.10 A and B High-Voltage Differential Mode (A_HVD_MODE and B_HVD_MODE)
These inputs inform the SYM53C140 that external drivers and receivers
are used in this particular application. The effect of this control is to
disable the LVD and single-ended modes of operation from the
corresponding port.
Table 2.2
Direction Control Signal Polarities
Signal Level
State
Effect
LOW = 0
Deasserted
Input signals into the SYM53C140
HIGH = 1
Asserted
Drive the SYM53C140 signals onto the bus
Table 2.3
HVD_MODE Control Signal Polarity
Signal Level
State
Effect
LOW = 0
Deasserted
SYM53C140 drivers function in single-ended or
LVD mode.
HIGH = 1
Asserted
High-Voltage Differential Signals and Controls
are enabled from the port.
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