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參數資料
| 型號： | SYM53C140 |
| 廠商： | LSI CORP |
| 元件分類： | 其它接口 |
| 英文描述： | Ultra2 SCSI Bus Expander(Ultra2 SCSI總線擴展器) |
| 中文描述： | SPECIALTY INTERFACE CIRCUIT, PQFP160 |
| 封裝： | 32 MM, PLASTIC, QFP-160 |
| 文件頁數： | 22/68頁 |
| 文件大?。?/td> | 928K |
| 代理商： | SYM53C140 |
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2-8
Functional Descriptions
1.
The bus is tested to be sure the data lines were not driven by the
SYM53C140. This is because valid data needs to be generated by
another node on the source bus to be passed through the
SYM53C140 to the load bus.
2.
The data is then leading edge filtered. The assertion edge is held for
a specified time to prevent any signal bounce. The duration is
controlled by the input signal.
3.
The next stage has two modes. One mode simply passes data
through. The other mode behaves like a large filter. The mode is
selected by the current state in the SYM53C140 State Machine that
tracks SCSI phases. The large filter mode is used when the Busy
(SBSY) and Select (SSEL) sources switch from side to side. This
output is then fed to the output driver which is a pull-down open
collector only.
4.
A parallel function ensures that bus (transmission line) recovery is
available for a specified time after the last signal deassertion on each
signal line.
2.1.7.4 Request and Acknowledge Control (SREQ and SACK)
A_SREQ, A_SACK, B_SREQ, and B_SACK are clock and control
signals. Their signal paths contain controls to guarantee minimum pulse
widths, filter edges, and does some retiming when used as data transfer
clocks. SREQ and SACK have paths from the A Side to the B Side and
from the B Side to the A Side. The received signal goes through the
following processing steps before being sent to the opposite bus:
1.
The asserted input signal is sensed and forwarded to the next stage
if the direction control permits it. The direction controls are developed
from state machines that are driven by the sequence of bus control
signals.
2.
The signal must then pass the test of not being generated by the
SYM53C140.
3.
In the A Side to B Side direction, the next stage is a leading edge
filter. This ensures that the output will not switch during the specified
hold time after the leading edge. The duration of the input signal
determines the duration of the output after the hold time. In the B
Side to A Side direction, the circuit guarantees a minimum pulse
width.
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相關代理商/技術參數 |
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| SYM53C141 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
| SYM53C400A | 制造商:SYMBIOS 功能描述: |
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| SYM53C876E(PBGA) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SCSI Bus Interface/Controller |
| SYM53C876E(PQFP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SCSI Bus Interface/Controller |
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