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參數(shù)資料
| 型號： | SYM53C140 |
| 廠商： | LSI CORP |
| 元件分類： | 其它接口 |
| 英文描述： | Ultra2 SCSI Bus Expander(Ultra2 SCSI總線擴展器) |
| 中文描述： | SPECIALTY INTERFACE CIRCUIT, PQFP160 |
| 封裝： | 32 MM, PLASTIC, QFP-160 |
| 文件頁數(shù)： | 18/68頁 |
| 文件大小： | 928K |
| 代理商： | SYM53C140 |
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2-4
Functional Descriptions
LVDlink technology is based on current drive. Its low output current
reduces the power needed to drive the SCSI bus. Therefore, the I/O
drivers can be integrated directly onto the chip. This reduces the cost and
complexity compared to traditional (high power) differential designs.
LVDlink lowers the amplitude of noise reflections and allows higher
transmission frequencies.
The LVDlink transceivers in side A and side B operate in the LVD, HVD
(external differential transceivers), or single-ended modes. The
SYM53C140 automatically detects the type of signal connected, based
on the voltages detected by A_DIFFSENS and B_DIFFSENS.
2.1.2 Retiming Logic
The SCSI signals, as they propagate from one side of the SYM53C140
to the other side, are processed by logic circuits that re-time the bus
signals, as needed, to guarantee or improve the required SCSI timings.
The logic circuitry is governed by the State Machine Controls that keep
track of SCSI phases, the location of initiator and target devices, and
various timing functions. In addition, the logic circuitry contains numerous
delay elements that are periodically calibrated by the Precision Delay
Control block in order to guarantee specified timing such as output pulse
widths, setup and hold times, and others.
2.1.3 State Machine Control
The State Machine Control keeps track of the SCSI bus phase protocol
and other internal operating conditions. This block provides signals to the
Retiming Logic that identify how to properly handle SCSI bus signal
retiming and protocol, based on observed bus conditions.
2.1.4 Precision Delay Control
The Precision Delay Control block provides calibration information to the
precision delay elements in the Retiming Logic block in order to maintain
precise timing as signals propagate through the device. As the
SYM53C140 operating conditions (such as voltage and temperature)
vary over time, the Precision Delay Control block will periodically update
the delay settings in the Retiming Logic to maintain constant and precise
control over bus timing.
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