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Samsung ASIC
v
STDL130
Contents
1
Introduction
1.1 Library Description................................................................................................................1-1
1.2 Features................................................................................................................................1-2
1.3 EDA Support .........................................................................................................................1-4
1.4 Product Family ......................................................................................................................1-4
1.4.1 Analog Core Cell .........................................................................................................1-4
1.4.2 Standard Logic Cells ...................................................................................................1-8
1.4.3 Compiled Macrocells ...................................................................................................1-8
1.4.4 Input/Output Cells........................................................................................................1-10
1.5
1.6
1.7
1.8
1.9
1.10 V
DD
/V
SS
Rules and Guidelines.............................................................................................1-36
1.11 Crystal Oscillator Considerations .........................................................................................1-43
Timings.................................................................................................................................1-13
Design for Test (DFT) Methodology......................................................................................1-21
Maximum Fanouts................................................................................................................1-24
Packages Capability by Pitch and Lead Count.....................................................................1-31
Power Dissipation.................................................................................................................1-32
2
Electrical Characteristics
DC Electrical Characteristics.........................................................................................................2-1
3
Internal Macrocells
Overview .......................................................................................................................................3-1
Summary Tables ...........................................................................................................................3-2
Logic Cells
AD2_LP/AD2D2_LP/AD2D4_LP/AD2D8_LP................................................................................3-14
AD2B_LP/AD2BD2_LP/AD2BD4_LP/AD2BD8_LP ......................................................................3-16
AD3_LP/AD3D2_LP/AD3D4_LP...................................................................................................3-18
AD4_LP/AD4D2_LP/AD4D4_LP...................................................................................................3-20
AD5_LP/AD5D2_LP/AD5D4_LP...................................................................................................3-22
ND2_LP/ND2D2_LP/ND2D4_LP/ND2D8_LP...............................................................................3-25
ND2B_LP/ND2BD2_LP/ND2BD4_LP/ND2BD8_LP......................................................................3-27
ND3_LP/ND3D2_LP/ND3D4_LP ..................................................................................................3-29
ND3B_LP/ND3BD2_LP/ND3BD4_LP/ND2BD8_LP......................................................................3-32
ND4_LP/ND4D2_LP/ND4D4_LP ..................................................................................................3-35