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Introduction
1.1 Library Description
Samsung ASIC
1-1
STDL130
1.1
Library
Description
STDL130isSamsung'snextgenerationStandardCelllibrarycontainingstandard
cells implemented in Samsung's 0.18
μ
m, L18L process technology. The focus of
Samsung’s L18L process is the lowest leakage current. The l
off
value of that
process is 3pA/um at typical conditions. This value is at least 30 to 40 times
smaller than that of the generic 0.18
μ
m process. Although the L18L process has
alittlebitpoorperformancethanthatofthegenericprocess,itcanextremelysave
the leakage current or standby powers for portable applications. Because the
L18L process is based on the generic 0.18
μ
m process, L18, it supports the
combined process in one chip that is the combination of L18L and L18 process
and it also supports all the IP cores and libraries of those process. It is an
excellently compensatory method for the poor performance.
The STDL130 library contains diverse application specific digital and analog IP
for System-on-Chip (SoC) applications. Samsung provides a full range of cells
within the STDL130 library to address the challenges of designing and producing
ultra low power as well as high density devices that take advantage of SoC
integration. With its reduced power dissipation and high density, STDL130 can
help reduce system cost for low leakage correct applications such as PDA,
CDMA and portable applications.
The STDL130 library supports gate counts of up to 23 million gates with 80%
usability. Logic and memory densities are respectively 2.6 and 3 times better than
STD110.
The STDL130 library also contains fully user configurable complied memories for
high density or low power applications. To get higher yield for SoC designs,
Samsung also contains the repairable compiled memory with row redundant
elements.
The STDL130 library also supports various of I/O interface voltages and
standards. I/O cells that drive 1.8V, 2.5V, and 3.3V are available as are 3.3V and
5V tolerant I/Os. Available I/O standards include LVTTL, LVCMOS, PCI, PCI-X,
OSC, ATA, AGP, PECL, SSTL2, GTLp, LVDS, and USB 1.1.
To better support SoC design, a robust collection of digital and analog IP cores
are available. Digital cores include the ARM7TDMI, ARM9TDMI, ARM920T, and
ARM940T from ARM Ltd., as well as the Teak and TeakLite DSP cores from the
DSP Group. Analog cores include ADCs, DACs, CODECs, and PLLs with various
bit configurations and frequency ranges. A thick oxide process option allows for
high resolution operation of analog cores with a 3.3V power supply.
In addition, the STDL130 library supports communication and data transmission
cores such as USB 1.1, IEEE1284, IEEE1394 link controller, UART, PCI
controller, PCMCIA controller and 10/100 ethernet MAC.
Samsung's design methodology offers a comprehensive timing driven design
flow including automated time budgeting, tight floor plan synthesis integration,
powerful timinganalysis, and timing driven layout. Our advanced characterization
flow provides accurate timing data and robust delay models for L18L, our 0.18
μ
m
very deep sub-micron process technology. Static verification methods, such as
static timing analysis and formal equivalence checking, provide an effective
verification methodology with a variety of simulators. Samsung's Design-for-Test
(DFT) methodology supports full and partial scan chain design, BIST, JTAG
boundary scan, and Built-in-Redundancy-Analysis (BIRA) for reparable SRAM.
Samsung provides a full set of test ready IP cores with an efficient core test
integration methodology.