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1.4 Product Family
Introduction
STDL130
1-6
Samsung ASIC
Sigma-Delta ADC/DAC
Samsung's L18L process offers high speed and high density, but reduced
accuracy and signal range (dynamic range) for analog components. Hence, an
exchange of digital complexity and resolution in time for resolution in signal
amplitude is needed. A good solution to this trade-off is an over sampling data
converter. An over sampling sigma-delta converter is ideal for slow speed (audio
band) applications. It's noise shaping (sigma-delta) feature produces a high
resolution output with a signal to noise ratio of 90 to 100dB.
In an ADC, an analog signal is converted to a differential signal and then filtered
with an anti-aliasing filter. A sigma delta modulator converts the signal into an
over sampled noise-shaping 1-bit pulse density modulated (PDM) signal. A digital
decimation filter then rejects the out-of-band noise and outputs a 16-bit high
resolution digital signal that is down sampled to the sampling rate, Fs. In a DAC,
digital data is over sampled by an interpolation filter and is converted to a
noise shaped 1-bit PDM signal through a digital sigma-delta modulator. An ana-
log SoC post filter rejects the out-of-band noise. An anti-image filter then rejects
the
sampling images and outputs a high resolution analog signal.
Phase Locked Loop
Samsung's PLL cores are implemented as an analog function to provide
frequency multiplication enabling SoC designers to synchronize chip level clock
networks to a common reference signal.
In the past, designers wishing to incorporate a PLL into a digital design had only
two options:
1) Use a special mixed signal process, typically an expensive process combing
bi-polar and CMOS processing on the same silicon, to implement the analog
functions.
2) Use and all digital PLL design requiring very large silicon area so that the PLL
could be implemented in a standard CMOS digital process. This type of PLL
design usually exhibits poor locking time.
Samsung's PLL cores are analog PLLs implemented on our standard digital
CMOS process. Advantages of Samsung's PLL cores are:
* Require only a few off-chip passive components to implement the PLL function.
* No need for an expensive mixed signal (bi-polar and CMOS) process.
* Provide a faster locking time than a full digital implementation.
* Have low jitter characteristics.
Customer Service and Technical Support
Samsung provides full support for our customers needing analog cores. Support
is provided through Samsung's worldwide Technology and Design Centers. In
addition, Samsung analog design engineers are available to design or customize
Samsung analog cores to meet specific customer needs. Since mixed signal de-
signisquitedifferentfromdigitaldesignintermsofdesigntechniques,layout,and
test methodology, Samsung provides a mixed signal technical guide describing
all development steps. In addition, each core is fully documented and is delivered
with a data sheet. The following is a description of analog core data sheets: