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參數(shù)資料
| 型號： | STA120 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | DIGITAL AUDIO INTERFACE RECEIVER |
| 中文描述： | 數(shù)字音頻接口接收機(jī) |
| 文件頁數(shù)： | 6/15頁 |
| 文件大小： | 183K |
| 代理商： | STA120 |
STA120
6/15
frequency detectors pull the VCO frequency within
the lock range of the PLL. When no digital audio
data is present, the VCO frequency is pulled to its
minimum value.
Figure 2. Jitter Attenuator Characteristics.
As a master, SCK is always MCK divided by four,
producing a frequency of 64 x FS. In the STA120,
FSYNC is always generated from the incoming
data stream. When FSYNC is generated from the
data its edges are extracted at times when in-
tersymbol interference is at a minimum. This pro-
vides a sample frequency clock that is as
spectrally pure as the digital audio source clock for
moderate length transmission lines.
STA120 DESCRIPTION
The STA120 does not need a microprocessor to
handle the non-audio data (although a micro may
be used with the C and U serial ports). Instead,
dedicated pins are available for the most important
channel status bits. The STA120 is a monolithic
CMOS circuits that receives and decodes digital
audio data which was encoded according to the
digital audio interface standards. It contains a
clock and data recovery utilizing an on-chip phase-
locked loop. The output data is output through a
configurable serial port that supports 14 formats.
The channel status and user data have their own
serial pins and the validity flag is OR'ed with the
ERF flag to provide a single pin, VERF, indicating
that the audio output may not be valid. This pin
may be used by interpolation filters that provide er-
ror correction.
Audio Serial Port
The audio serial port is used primarily to output au-
dio data and consists of three pins: SCK, FSYNC
and SDATA. These pins are configured via four
control pins: M0, M1,M2,and M3.M3 selects be-
tween eight normal serial formats (M3 = 0), and six
special formats (M3 = 1).
Normal Modes (M3 = 0)
When M3 is low, the normal serial port formats
shown in Figure 3 are selected using M2, M1 and
M0. These formats are also listed in Table 1
wherein the first word part the format number (Out-
In) indicates whether FSYNC and SCK are outputs
from the STA120 or are inputs.
The next word (L/R-WSYNC) indicates whether
FSYNC indicates the particular channel or just de-
lineates each word. If an error occurs (ERF=1)
while using one of these formats, the previous val-
id audio data for that channel will be output.
If the STA120 is not locked, the last sample is re-
peated at the output. In some modes FSYNC and
SCK are outputs and in others they are inputs. In
Table 3, LSBJ is short for LSB justified where the
LSB is justified to the end of the audio frame and
the MSB varies with word length. As outputs the
STA120 generates 32 SCK periods per audio
sample (64 per stereo sample) and, as inputs, 32
SCK periods must be provided per audio sample.
When FSYNC and SCK are inputs, one stereo
sample is double buffered. For those modes which
output 24 bits of audio data, the auxiliary bits will
be included. If the auxiliary bits are not used for
audio data, they must be masked off.
1
10
100
1000
(KHz)
100
75
50
25
(dB)
D97AU612
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參數(shù)描述 |
|---|---|
| STA120D | 功能描述:音頻 DSP Audio Interfce Recvr RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
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