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參數(shù)資料
| 型號： | STA120 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | DIGITAL AUDIO INTERFACE RECEIVER |
| 中文描述： | 數(shù)字音頻接口接收機(jī) |
| 文件頁數(shù)： | 2/15頁 |
| 文件大小： | 183K |
| 代理商： | STA120 |
STA120
2/15
ABSOLUTE MAXIMUM RATINGS
PIN CONNECTIONS
(Top view)
Symbol
Parameter
Value
Unit
V
D+
, V
A+
Power Supply Voltage
4
V
V
IN
Input Voltage ( excluding pins 9, 10)
-0.3 to V
D
+ +0.3
V
T
amb
Ambient Operating Temperature (power applied)
-30 to +85
°C
T
stg
Storage Temperature
-40 to 150
°C
PINS DESCRIPTION
N.
Name
Description
Power Supply
7
8
21
V
D+
DGND
AGND
Positive Digital Power.Positive supply for the digital section. Nominally 3.3V.
Digital Ground.Ground for the digital section.
Analog Ground.Ground for the analog section. AGND should be connected to same ground as
DGND.
Positive Analog Power.Positive supply for the analog section. Nominally 3.3V.
Audio Output Interface
11
FSYNC
Frame Sync.Delineates the serial data and may indicate the particular channel, left or right and
may be an input or output. The format is based on M0, M1, M2 and M3 pins.
12
SCK
Serial Clock.Serial clock for SDATA pin which can be configured (via the M0, M1, M2 and M3
pins) as an input or output and can sample data on the rising or falling edge. As an output, SCK
will generate 32 clocks for every audio sample. As an input, 32 SCK periods per audio sample
must be provided in all normal modes.
17, 18,
23, 24
M1, M0
to SDATA.
26
SDATA
Serial Data. Audio data serial output pin.
22
V
A+
M2, M3,
Serial Port Mode Selects.Selects the format of Fsync and the sample edge of SCK with respect
C0/E0
VD+
DGND
RXP
RXN
SCK
FSYNC
CS12/FCK
U
1
3
2
4
5
6
7
8
9
CBL
SEL
M3
MCK
M2
FILT
AGND
VA+
M0
23
22
21
20
19
17
18
16
15
D97AU609A
10
11
12
13
14
28
27
26
25
24
C
Cd/F1
Cc/F0
Cb/E2
Ca/E1
M1
ERF
SDATA
Ce/F2
VERF
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STA120D | 功能描述:音頻 DSP Audio Interfce Recvr RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
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