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參數(shù)資料
| 型號： | STA120 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | DIGITAL AUDIO INTERFACE RECEIVER |
| 中文描述： | 數(shù)字音頻接口接收機(jī) |
| 文件頁數(shù)： | 5/15頁 |
| 文件大?。?/td> | 183K |
| 代理商： | STA120 |
5/15
STA120
Figure 1. Circuit Diagram
GENERAL DESCRIPTION
The STA120 is a monolithic CMOS circuit that receives and decodes audio and digital data according to
the AES/EBU, IEC 958, S/PDIF, and EIAJ CP-340/1201 interface standards.
It contains a RS422 line receiver and Phase-Locked Loops (PLL) that recovers the clock and synchroni-
zation signals and de-multiplexes the audio and digital data. The STA120 de-multiplexes the channel sta-
tus, user and validity information directly to serial output pins with dedicated pins for the most important
channel status bits.
Line Receiver
The line receiver can decode differential as well as single ended inputs. The receiver consits of a differ-
ential input Schmitt trigger with 50mV of hysteresis. The hysteresis prevents noisy signals from corrupting
the phase detector. Appendix A contains more information on how to configure the line receivers for dif-
ferential and single ended signals.
Clocks and Jitter Attenuation
The primary function of this chip is to recover audio data and low jitter clocks from a digital audio trans-
mission line. The clocks that can be generated are MCK (256xFS), SCK (64xFS), and FSYNC (FS or
2xFS). MCK is the output of the voltage controlled oscillator which is a component of the PLL. The PLL
consists of phase and frequency detectors, a second-order loop filter, and a voltage controlled oscillator.
All components of the PLL are on chip with the exception of a resistor and capacitors used in the loop filter.
This filter is connected between the FILT pin and AGND. The closed-loop transfer function, which speci-
fies the PLL's jitter attenuation characteristics, is shown in Figure 2.
The loop will begin to attenuate jitter at approximately 25kHz with another pole at 80kHz and will have
50dB of attenuation by 1MHz. Since most data jitter introduced by the transmission line is high in frequen-
cy, it will be strongly attenuated.
Multiple frequency detectors are used to minimize the time it takes the PLL to lock to the incoming data
stream and to prevent false lock conditions. When the PLL is not locked to the incoming data stream, the
10
AUDIO
DATA
PROCESSOR
μ
CONTROLLER
or
LOGIC
RECEIVER
CIRCUIT
(See Appendix A)
RXN
SCK
FSYNC
7
VD+
STA120
3.3V
ANALOG
22
VA+
AGND
21
0.1
μ
F
VERF
19
SDATA
26
11
C
1
CBL
15
D97AU611
3.3V
DIGITAL
0.1
μ
F
20
FILT
15nF
0.47
μ
F
330
8
DGND
U
14
MCK
28
12
9
RXP
CHANNEL STATUS
and/or
ERROR/FREQUENCY
REPORTING
13
CS12/FCK
16
SEL
25
ERF
6
C/E-F bits
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STA120D | 功能描述:音頻 DSP Audio Interfce Recvr RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| STA120D13TR | 功能描述:音頻 DSP Digital Audio Intrfc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| STA120DJ | 制造商:STMicroelectronics 功能描述:DGTL AUD INTRFC RCVR 28SOIC - Rail/Tube |
| STA120DJ13TR | 功能描述:音頻 DSP Digital audio interface receiver RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| STA1210 | 制造商:M.E.C. Relays 功能描述: |
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