參數(shù)資料
型號(hào)： ST92163R4
英文描述： 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS. 20K ROM. 2K RAM. I 2 C. SCI. & MFT
中文描述： 16位產(chǎn)品全速USB微控制器，16終點(diǎn)復(fù)合設(shè)備。 20,000光盤。 2K的RAM。余2長(zhǎng)脊髓損傷。
文件頁(yè)數(shù)： 74/230頁(yè)
文件大?。?/td> 2743K
代理商： ST92163R4
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ST92163 - ON-CHIP DIRECT MEMORY ACCESS (DMA)
4.6 DMA REGISTERS
As each peripheral DMA channel has its own spe-
cific control registers, the following register list
should be considered as a general example. The
names and register bit allocations shown here
may be different from those found in the peripheral
chapters.
DMA COUNTER POINTER REGISTER (DCPR)
Read/Write
Address set by Peripheral
Reset value: undefined
Bit 7:1 =
C[7:1]
: DMA Transaction Counter Point-
er.
Software should write the pointer to the DMA
Transaction Counter in these bits.
Bit 0 =
RM
: Register File/Memory Selector.
This bit is set and cleared by software.
0: DMA transactions are with memory (see also
DAPR.DP)
1: DMA transactions are with the Register File
GENERIC EXTERNAL PERIPHERAL INTER-
RUPT AND DMA CONTROL (IDCR)
Read/Write
Address set by Peripheral
Reset value: undefined
Bit 5 =
IP
: Interrupt Pending
This bit is set by hardware when the Trigger Event
occurs. It is cleared by hardware when the request
is acknowledged. It can be set/cleared by software
in order to generate/cancel a pending request.
0: No interrupt pending
1: Interrupt pending
Bit 4 =
DM
: DMA Request Mask
This bit is set and cleared by software. It is also
cleared when the transaction counter reaches
zero (unless SWAP mode is active).
0: No DMA request is generated when IP is set.
1: DMA request is generated when IP is set
Bit 3 =
IM
: End of blockInterrupt Mask.
This bit is set and cleared by software.
0: No End of block interrupt request is generated
when IP is set
1: End of Block interrupt is generated when IP is
set. DMA requests depend on the DM bit value
as shown in the table below.
Bit 2:0 =
PRL[2:0]
: SourcePriority Level
These bits are set and cleared by software. Refer
to Section 4.2 for a description of priority levels.
DMA ADDRESS POINTER REGISTER (DAPR)
Read/Write
Address set by Peripheral
Reset value: undefined
Bit 7:1 =
A[7:1]
: DMA Address Register(s) Pointer
Software should write the pointer to the DMA Ad-
dress Register(s) in these bits.
Bit 0 =
PS
: Memory Segment Pointer Selector:
This bit is set and cleared by software. It is only
meaningful if DCPR.RM=0.
0: The ISR register is used to extend the address
of data transferred by DMA (see MMU chapter).
1: The DMASR register is used to extend the ad-
dress of data transferred by DMA (see MMU
chapter).
7
0
C7
C6
C5
C4
C3
C2
C1
RM
7
0
IP
DM
IM
PRL2 PRL1 PRL0
DM IM Meaning
1
0
A DMA request generated without End of Block
interrupt when IP=1
A DMA request generated with End of Block in-
terrupt when IP=1
No End of block interrupt or DMA request is
generated when IP=1
An End of block Interrupt is generated without
associated DMA request (not used)
1
1
0
0
0
1
PRL2 PRL1 PRL0 Source Priority Level
0
0
0
0 Highest
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7 Lowest
7
0
A7
A6
A5
A4
A3
A2
A1
PS
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST92163R4B0 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT
ST92163R4B0E 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT
ST92163R4B0L 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT
ST92163R4B0V 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT
ST92163R4B1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT
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