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參數(shù)資料
| 型號(hào)： | ST92163R4 |
| 英文描述： | 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS. 20K ROM. 2K RAM. I 2 C. SCI. & MFT |
| 中文描述： | 16位產(chǎn)品全速USB微控制器，16終點(diǎn)復(fù)合設(shè)備。 20,000光盤。 2K的RAM。余2長脊髓損傷。 |
| 文件頁數(shù)： | 146/230頁 |
| 文件大?。?/td> | 2743K |
| 代理商： | ST92163R4 |
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ST92163 - USB PERIPHERAL (USB)
USB INTERFACE (
Cont’d
)
DEVICE n ADDRESS (DADDRn)
R240 to R247 - Read/Write
Register page: 15
Reset Value: 0000 0000 (00h)
Note:
This register is also reset when a USB reset
is received from the USB bus or forced through bit
FRES in the USBCTLR register.
Bit 7 =
EF
:
Enable Function
.
Set by software to enable the USB function whose
address is contained in the following ADD[6:0]
bits.
0: Function disabled
1: Function enabled
Bits 6:0 =
ADD[6:0]
:
Device Address
.
Software must write into these bits the USB device
address assigned by the host PC during the enu-
meration.
ENDPOINT n REGISTER A (EPnRA)
(TRANSMISSION)
R240-R254 (even)
Read/Write
Register pages: 4 & 5
Reset value: 0000 0000 (00h)
These registers are used for controlling data trans-
mission. They are also reset when a USB reset is
received or forced through the FRES bit in the US-
BCTLR register.
Note:
The CTR bits are not affected by a USB re-
set
Each endpoint has its EPnRA register where n is
the endpoint identifier in the range 0 to 15.
Bit 7 =
CTR
:
Correct Transfer
.
Set by hardware when a transaction is successful-
ly completed on this endpoint; software can only
clear this bit.
0: No correct transfer occurred
1: Correct transfer occurred
Note:
A transaction ended with a NAK or STALL
handshake does not set this bit, since no data is
actually transferred, as in the case of protocol er-
rors or data toggle mismatches. The CTR bit is
also used to perform flow control: while CTR=1, a
valid endpoint answers NAK to every transaction
addressed to it (except SETUP requests which are
simply ignored) until the application software ac-
knowledges the CTR event, resetting this bit. This
does not apply to isochronous endpoints where no
handshake phase is used.
Bit 6 =
DTOG_TX
:
Data Toggle, for transmission
transfers
.
If the endpoint is non-isochronous, this bit contains
the required value of the data toggle bit
(0=DATA0, 1=DATA1) for the next data packet to
be transmitted. Hardware toggles this bit when the
ACK handshake is received from the USB host,
following a data packet transmission. If the end-
point is defined as a control one, hardware sets
this bit to 1 on reception of a SETUP PID ad-
dressed to this endpoint.
If the endpoint is isochronous, this bit is used to
support DMA buffer swapping since no data tog-
gling is used for this sort of endpoint and only
DATA0 packet are transmitted. Hardware toggles
this bit just after the end of data packet transmis-
sion, since no handshake is used for isochronous
transfers.
Note:
this bit can be also written by software to in-
itialize it (mandatory when the endpoint is not a
control endpoint) or to force specific data toggle/
DMA buffer usage.
7
0
EF
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
7
0
CTR
DTOG_
TX
STAT_
TX1
STAT_
TX0
PIDR1 PIDR0
CEP
ISO
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST92163R4B0 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT |
| ST92163R4B0E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT |
| ST92163R4B0L | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT |
| ST92163R4B0V | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT |
| ST92163R4B1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT |
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