參數(shù)資料
型號(hào): ST70134A
英文描述: ASCOT (TM) INTEGRATED ADSL CMOS ANALOG FRONT-END CIRCUIT
中文描述: 阿斯科特(TM)集成寬頻CMOS模擬前端電路
文件頁(yè)數(shù): 9/22頁(yè)
文件大小: 154K
代理商: ST70134A
ST70134A
9/22
Figure 5 :
HC Filter Mask for RX
Note: The total RX path (including ADC) group delay distortion is 16
μ
s (i.e. = 15
μ
s + 1
μ
s of ADC)
Linearity of RX
Linearity of the RX analog path is defined by the IM3 product of two sinusoidal signals with frequencies f1
and f2 and each with 0.5Vpd amplitude (total
1Vpd) at the output of the RX - AGC amplifier (i.e: before
the ADC) for the case of minimal AGC setting.
Table 7 lists the RX path intermodulation distortion (as S/IM3 ratio) in downstream and upstream band-
width.
Table 7 :
Linearity of RX
Power Supply Rejection
The noise on the power supplies for the RX path must be lower than the following: <50mVrms in band
white noise for any AVDD.
In this case, PSR (power supply rejection) of ST70134 RX path is lower than -43dB.
f1 (0.5Vpd)
f2 (0.5Vpd)
300kHz
200kHz
500kHz
400kHz
700kHz
600kHz
S/IM3
(AGC = 0dB)
59.5dB @ 100kHz
53.5dB @ 400kHz
43.5dB @ 700kHz
42.5dB @ 800kHz
59.5dB @ 300kHz
48.0dB @ 600kHz
48.0dB @ 500kHz
42.5dB @ 800kHz
Table 8 :
RX Filter to A/D Interface
RX filter to A/D maximal level:
1Vpd = full scale of A/D
Table 9 :
A/D Converters
Numbers of bits:
12bits
Minimum resolution of the A/D converter
11bits
Linearity error of the A/D converter
<1LSB (out of 12bits)
Full scale input range:
1 Vpdif ±5%
Sampling rate:
8.832MHz (or 4.416MHz in OSR = 2 mode)
Maximum attenuation at 1.1MHz:
<0.5dB without in-band ripple
Maximum group delay:
<3
μ
s
Maximum group delay distortion:
<1
μ
s
5dB 36dB 50dB
±1dB
0dB
30
1104 2208 7728 16
560
kHz
Amplitude
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