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參數(shù)資料
| 型號(hào)： | ST70134A |
| 英文描述： | ASCOT (TM) INTEGRATED ADSL CMOS ANALOG FRONT-END CIRCUIT |
| 中文描述： | 阿斯科特（TM）集成寬頻CMOS模擬前端電路 |
| 文件頁(yè)數(shù)： | 17/22頁(yè) |
| 文件大?。?/td> | 154K |
| 代理商： | ST70134A |
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ST70134A
17/22
Receive / Transmit Interface Timing
The interface is a quadruple (RX, TX) nibble -
serial interface running at 8.8MHz sampling (nor-
mal mode). The data are represented in 16bits
format, and transferred in groups of 4 bits (nib-
bles). The LSBs are transferred first. The
ST70134 generates a nibble clock (CLKM master
clock in normal mode, CLKNIB in OSR = 2 mode)
and word signals shared by the three interfaces.
Data is transmitted on the rising edge of the mas-
ter clock (CLKM/CLKNIB) and sampled on the
falling edge of CLKM/CLKNIB. This holds for the
data stream from ST70134 and from the digital
processor.
Data, CLWD setup and hold times are 5ns with
reference to the falling edge of CLKM/CLKNIB.
(not floating).
Data is transmitted on the rising edge of the mas-
ter clock (CLKM/CLKNIB) and sampled on the low
going edge of CLKM/CLKNIB. This holds for the
data stream from ST70134 and from the digital
processor.Data, CLWD setup and hold times are
5ns with reference to the falling edge of CLKM/
CLKNIB. (not floating).
Power Down
When pin Pdown = "1", the chip is set in power
down mode. As the Pdown signal is synchro-
nously sampled, minimum duration is 2 periods of
the 35MHz clock. In this mode all analog func-
tional blocks are deactivated except: preamplifiers
(TX), clock circuits for output clock CLKM. Pdown
will not affect the digital part of the chip. Anyway,
after a Pdown transition, the digital part status, is
updated after 3 clock periods (worst case).
The chip is activated when Pdown = "0".
In power down mode the following conditions
hold:
– Output voltages at TXP/TXN = AGND
– Preamplifier is on with maximum gain setting
(0dB), (digital gain setting coefficients are over-
ruled)
– The XTAL output clock on pin CLKM keeps running.
– All digital setting are retained.
– Digital output on pins RXDx don't care(not floating).
In power-down mode the power consumption is
100mW.
Following external conditions are added:
– Clock pin CLW is running.
– CTRLIN signals can still be allowed.
– AGND remains at AVDD/2 (circuit is powered up)
– Input signal at TXDx inputs are not strobed.
The Pdown signal controls asynchronously the
power-down of each analog module:
– After a few
μ
s the analog channel is functional
– After about 100ms the analog channel delivers
full performance
Reset Function
The reset function is implied when the RESETN
pin is at a low voltage input level. In this condition,
the reset function can be easily used for power up
reset conditions.
Detailed Description
During reset: (reset is asynchronous, tenths of ns
are enough to put the IC in reset).
All clock outputs are deactivated and put to logical
"1" (except for the XTAL and master clock CLKM).
After reset: (4 clock periods after reset transition,
as worst case).
– OSR = 4
– All analog gains (RX, TX) are set to minimum value
– Nominal filter frequency bands (138kHz,
1.104MHz)
– LNA input = "11" (max. attenuation)
– VCO dac disabled
Digital outputs are placed in don't care condition
(non-floating).
N.B. If a Xtal oscillator is used, the RESET must
be released at last 10
μ
s after power-on, to ensure
a correct duty cycle for the clk35 clock signal.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST70134-ST70135A | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:ASCOT ADSL MODEM CHIP SET FOR CPE |
| ST70134TR | 功能描述:電信線路管理 IC ADSL DMT Transceiver RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| ST70135 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:ASCOTTM DMT TRANSCEIVER |
| ST70135A | 制造商:STMicroelectronics 功能描述:Modem Chip Single 144-Pin PQFP |
| ST70136 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:CPE ADSL ANALOG FRONT END |
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