參數(shù)資料
型號(hào)： ST70134A
英文描述： ASCOT (TM) INTEGRATED ADSL CMOS ANALOG FRONT-END CIRCUIT
中文描述： 阿斯科特（TM）集成寬頻CMOS模擬前端電路
文件頁(yè)數(shù)： 5/22頁(yè)
文件大?。?/td> 154K
代理商： ST70134A
ST70134A
5/22
Table 2 :
Pin Functions
Numbers
Name
Function
PCB connection
Supply
ANALOG INTERFACE
24
25
26
31
32
38
44
45
46
47
48
49
VRAP
VREF
VRAN
TXP
TXN
AGND
VCOC
GC0
GC1
RXN0
RXP0
RXN1
Positive Voltage Reference ADC
Ground Reference ADC
Negative Voltage Reference ADC
Pre Driver Output
Pre Driver Output
Virtual Analog Ground (AVDD/2 = 1.65V)
VCODAC Time Constant Capacitor
External Gain Control Output LSB
External Gain Control Output MSB
Analog Receive Negative Input Gain 0
Analog Receive Positive Input Gain 0
Analog Receive Negative Input Gain 1
(Most Sensitive Input)
Analog Receive Positive Input Gain 1
(Most Sensitive Input)
Current Reference TX DAC/DACE
Current Reference VCO DAC
VXCO Control Current
XTAL Oscillator Input Pin
XTAL Oscillator Output Pin
Decoupling network
Decoupling network
Decoupling network
Line driver input
Line driver input
Decoupling network
VCODAC cap.
-
-
Echo filter output
Echo filter output
Echo filter output
AVDD3
AVDD3
AVDD3
AVDD4
AVDD4
AVDD5
AVDD5
AVDD5
AVDD5
AVDD5
AVDD5
AVDD5
50
RXP1
Echo filter output
AVDD5
53
55
56
59
60
IREF
IVCO
VCXO
XTALI
XTALO
Decoupling network
VCO bias network
VCXO filter
Crystal + varicap
Crystal + varicap
AVDD2
AVDD1
AVDD1
AVDD1
AVDD1
DIGITAL INTERFACE
1
2
7
9
10
TX1
TX0
CTRLIN
CLKM
CLNIB
Digital Transmit Input, Parallel Data
Digital Transmit Input, Parallel Data
Serial Data Input (Settings)
Master Clock Output, f = 35.328MHz
Nibble Clock Output, f = 17.664MHz
(OSR = 2) or ground (OSR = 4)
Word Clock Output, f = 8.832/4.416MHz
Digital Receive Output, Parallel Data
Digital Receive Output, Parallel Data
Digital Receive Output, Parallel Data
Digital Receive Output, Parallel Data
Power Down Select, "1" = Power Down
Reset Pin (Active Low)
General Purpose Output 0 (on AVDD 1)
General Purpose Output 1 (on AVDD 1)
General Purpose Output 2 (on AVDD 1)
Digital Transmit Input, Parallel Data
Digital Transmit Input, Parallel Data
RESERVED
RESERVED
-
-
Async Interface
Load = CL<30pF
Load = CL<30pF
DVDD2
DVDD2
DVDD2
DVDD2
DVDD2
11
12
13
14
15
18
20
22
33
43
63
64
CLWD
RX3
RX2
RX1
RX0
PDOWN
RESETN
GP0
GP1
GP2
TX3
TX2
RES
RES
Load = CL<30pF
Load = CL<30pF
Load = CL<30pF
Load = CL<30pF
Load = CL<30pF
Power Down Input
RC- Reset
Echo filter output
Echo filter output
Echo filter output
Load = CL<30pF
Load = CL<30pF
Must Be Connected to DVSS (Input)
Must Be Connected to AVSS (Input)
DVDD2
DVDD2
DVDD2
DVDD2
DVDD2
DVDD2
DVDD2
AVDD
AVDD
AVDD
DVDD2
DVDD2
-
-
19, 21
36, 37, 39,
40, 57
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST70134-ST70135A 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:ASCOT ADSL MODEM CHIP SET FOR CPE
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