參數(shù)資料
型號: ST70134A
英文描述: ASCOT (TM) INTEGRATED ADSL CMOS ANALOG FRONT-END CIRCUIT
中文描述: 阿斯科特(TM)集成寬頻CMOS模擬前端電路
文件頁數(shù): 12/22頁
文件大小: 154K
代理商: ST70134A
ST70134A
12/22
The information coming from the digital processor via the CTRLIN path is used to drive an 8-bit DAC
which generates a control current. This current is externally converted and filtered to generate the
required control voltage (range:-15V to 0.5V) for the varicap. The VCXO circuit characteristics are given
in Table 15.
Table 15 :
VCXO circuit Characteristics
N.B: frequency tuning range is proportional to the crystal dynamic capacitance Cm.
Figure 7 :
Principle of VCXO control
The tuning must be monotonic with 8-bit resolution with the worst-case tuning step of <2ppm/LSB (8-bit).
The time constant of the tuning must be variable from 5s to 10s through an external capacitor Cs (R =
1M
±30%). This determines the speed of the VCXO in normal operation (slow speed in "show time")
with filtered VCXO. For faster tracking, the previous filter is not used and the speed depends on CtRt.
DIGITAL INTERFACE
Control Interface
The digital setting codes for the ST70134 configuration are sent over a serial line (CTRLIN) using the
word clock (CLWD).
The data burst is composed of 16 bits from which the first bit is used as start bit ('0'), the three LSBs being
used to identify the data contained in the 12 remaining bits.
Symbol
Parameter
Minimum
Nominal
Maximum
Note
f
abs
f
range
IO
Absolute frequency accuracy
-15ppm
35.328MHz
+15ppm
Frequency Tuning Range
±50ppm
VCXO Output Current
100
μ
A
Rref = 16.5k
AVDD = 3.3V
AVDD = 3.3V
Ii
Reference Input Current
100
μ
A
1mA
DAC
8 Bits
1M
±
30%
Filtered VCXO
(see CTRLIN table)
44
VCOC
Cs
AVDD
7
CTRLIN
55
IVCO
AVDD
Rref
AVDD/22 ÷ AVDD/2
li
56
VCXO
Clk35
60
59
Cp
XTALI
XTALO
Ct
Rt
AGND
Io = li
-15V
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