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參數(shù)資料
| 型號(hào)： | ST623X-EMU2 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | REAL TIME EMULATION DEVELOPMENT TOOLS FOR ST6 MCU FAMILY |
| 中文描述： | 實(shí)時(shí)仿真開(kāi)發(fā)工具，ST6單片機(jī)系列 |
| 文件頁(yè)數(shù)： | 61/86頁(yè) |
| 文件大?。?/td> | 531K |
| 代理商： | ST623X-EMU2 |
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ST62T30B ST62E30B
5.4.2 CLOCK GENERATION
The UART contains a built-in divider of the MCU
internal clock for most common Baud Rates as
shown in Table 20. Other baud rate values can be
calculated from the chosen oscillator frequency di-
vided by the Divisor value shown.
The divided clock provides a frequency that is 8
times the desired baud rate. This allows the Data
reception mechanism to provide a 2 to 1 majority
voting system to determine the logic state of the
asynchronous incoming serial logic bit by taking 3
timed samples within the 8 time states.
The bits not sampled provide a buffer to compen-
sate for frequency offsets between sender and re-
ceiver.
5.4.3 DATA TRANSMISSION
Transmission is fixed to a format of one start bit,
nine data bits and one stop bit. The start and stop
bits areautomatically generated by the UART. The
nine databits are under control of the user and are
flexible in use. Bits 0..7 are typically used as data
bits while bit 9 is typically used as parity, but can
also be a 9th data bit or an additional Stop bit. As
parity is not generated by the UART, it should be
calculated by program and inserted in the appro-
priate position of the data (i.e as bit 7 for 7-bit data,
with Bit 9 set to 1 giving two effective stop bits or
as the independent bit 9).
Figure 35. Data Sampling Points
The character options are summarised in the fol-
lowing table.
Table 19. Character Options
Bit 9 remains in the state programmed for consec-
utive transmissions until changed by the user or
until a character is received when the state of this
bit is changed to that of the incoming bit 9. The
recommended procedure is thus to set thevalue of
this bit before transmission is started.
Transmission is started by writing to the Data Reg-
ister (theBaud Rateand Bit 9 should be set before
this action). The UARTOE signal switches the out-
put multiplexer to the UART output and a start bit
is sent (a 0 for one bit time) followed by the 8 data
values (lsb first) and the value of the Bit9 bit. The
output is then setto 1 for a period of one bit timeto
generate a Stop bit, and then the UARTOE signal
returns the TXD1 line to its alternate I/O function.
The end of transmission is flagged by setting
TXMT to 1 and an interrupt is generated if ena-
bled. The TXMT flag is reset by writing a 0 to the
bit position, it is also cleared automatically when a
new character is written to the Data Register.
TXMT can be set to 1 by software to generate a
software interrupt so care must be taken in manip-
ulating the Control Register.
Figure 36. Character Format
VR02010
1 BIT
0
1
2
3
4
5
6
7
8
SAMPLES
Start Bit
Start Bit
Start Bit
Start Bit
8 Data
9 Data
8 Data
7 Data
1 Software Parity
No Parity
No Parity
1 Software Parity
1 Stop
1 Stop
2 Stop
2 Stop
VR02012
POSITION
1
2
8
10
BIT
BIT
START
STOP
BIT
POSSIBLE
NEXT
CHARACTER
START
D0
D1
D7 D8
START OF DATA
9
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| ST623X-KIT/110 | 功能描述:開(kāi)發(fā)板和工具包 - 其他處理器 ST623X Starter Kit RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
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