- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372308 > ST623X-EMU2 (意法半導(dǎo)體) REAL TIME EMULATION DEVELOPMENT TOOLS FOR ST6 MCU FAMILY PDF資料下載
參數(shù)資料
| 型號(hào)： | ST623X-EMU2 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | REAL TIME EMULATION DEVELOPMENT TOOLS FOR ST6 MCU FAMILY |
| 中文描述： | 實(shí)時(shí)仿真開發(fā)工具，ST6單片機(jī)系列 |
| 文件頁數(shù)： | 54/86頁 |
| 文件大?。?/td> | 531K |
| 代理商： | ST623X-EMU2 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁當(dāng)前第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁
54/86
ST62T30B ST62E30B
5.2.5 CONTROL REGISTERS
Status Control Register 1 (SCR1)
Address: E8h - Read/Write/Clear only
Bits 7 & 6 =
PSC2..PSC1
. Clock Prescaler These
bits define the prescaler options for the prescaler
to the Counter Register according to the following
table.
The Prescaler must be disabled (PSC2 = 0, PSC1
= 0) before a new prescaler factor is set if the
counter is running (after a hardware reset the
prescaler is automatically disabled).
To avoid inconsistencies in timing, the prescaler
factor should be set first, and then the counter
started.
Bit 5 =
RELOAD
. Reload enabled. When set this
bit enables reload from RLCP register intoCT reg-
ister. On the contrary, if RELOAD is cleared,
RLCP is used as target for capture from the coun-
ter CT register.
Bit 4 =
RUNRES
. Run/Reset This bit enables the
RUN or RESET operation of the ARTIMER.
If 0, the counter CT is cleared to zero, and is
stopped. Setting this bit to 1 permits the startup of
the counter, and enables the synchronisation cir-
cuits for the timer inputs CP1 and CP2.
Bit 3 =
OVFIEN
. Overflow Int. Enable The Over-
flow Interrupt is masked when this bit is 0.
Setting the bit to 1 enables the overflow flag to set
the ARTIMER interrupt.
Bit 2 =
OVFFLG
. When this bit is 0, no overflow
has occurred since the last clear of this bit. If the
bit is at 1, an overflow has occurred.
This bit cannot be set by program, only cleared.
Bit 1 =
OVFMD
. The Overflow Output mode is set
by this bit; when 0, the overflow output is run in set
mode (OVF will be set on the first overflow event,
and will be reset when OVFFLG is cleared). When
1 the overflow output is in toggle mode; OVF tog-
gles its state on every overflow event (independ-
ent to the state of OVFFLG).
Bit 0 = This bit is reserved and must be set to 0.
Status Control Register 2 (SCR2)
Address: E1h - Read/Write/Clear only
Bit 7 = Reserved. Must be kept cleared.
Bit 6 =
CP1ERR
. CP1 Error Flag This bit is set to
1 if a new CP1 event has taken place since
CP1FLG was set to signal an error condition, it is 0
if there has been no event.
It is recommended to clear CP1ERR at any time
that CP1FLG is cleared, as further CP1 events
cannot be recognised if CP1ERR is set. This bit
cannot bet set by write, only cleared.
Bit 5 =
CP2ERR
. CP1 Error Flag This bit is set to
1 if a new CP2 event has taken place since
CP2FLG was set to signal an error condition, it is 0
if there has been no event.
It is recommended to clear CP2ERR at any time
that CP2FLG is cleared, as further CP2 events
cannot be recognised if CP2ERR is set. This bit
cannot bet set by write, only cleared.
Bit 4 =
CP1IEN
. CP1 Interrupt Enable. CP1 The
Capture 1 Interrupt is masked when this bit is 0.
Setting the bit to 1 enables the CP1 event flag
CP1FLG to set the ARTIMER interrupt.
Bit 3 =
CP1FLG
. CP1 Interrupt Flag. When this bit
is 0, no CP1 event has occurred since the last
clear of this bit. If the bit is at 1, a CP1 event has
occurred.
This bit cannot be set by program, only cleared.
Bit 2 =
CP1POL
. CP1 Edge Polarity Select
CP1POL defines the polarity fortriggering the CP1
event.
A 0 defines the action on a falling edge on theCP1
input, a 1 on a rising edge.
Bit 1 & 0 =
RLDSEL2..RLDSEL1
. Reload Source
Select These bits define the source for the reload
events; they do not affect the operation of the cap-
ture modes.
7
0
PSC2
PSC1
RELOAD RUNRES
OVFIEN OVFFLG OVFMD
-
PSC2
PSC1
Function
0
0
Clock Disabled (prescaler and counter
stopped
Prescale by 1
Prescale by 4
Prescale by 16
0
1
1
1
0
1
7
0
-
CP1ERR CP2ERR CP1IEN
CP1FLG CP1POL
RLDSEL2 RLDSEL1
RLDSEL2 RLDSEL1
Function
0
0
Reload and startup triggered by
RUNRES
Reload triggered by every CP1
event
Reload triggered by every CP2
event
Reload disabled
0
1
1
0
1
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST62T65BB3 | 8-BIT MICROCONTROLLER |
| ST62T65BB6 | 8-BIT MICROCONTROLLER |
| ST62T65BM3 | 8-BIT MICROCONTROLLER |
| ST62T65BM6 | 8-BIT MICROCONTROLLER |
| ST62E65BF1 | 8-BIT MICROCONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST623X-KIT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:STARTER KIT DATASHEET FOR ST6230 |
| ST623X-KIT/110 | 功能描述:開發(fā)板和工具包 - 其他處理器 ST623X Starter Kit RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| ST623X-KIT/220 | 制造商:STMicroelectronics 功能描述:ST Development Kit, Including ST623X Starter Kit, Development Software CD-ROM, Parallel Cable, Power Supply, Window Development Devices ST62E30BF1, ST (More...) |
| ST623X-KIT/UK | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:STARTER KIT AB 8K BYTE |
| ST-6-24 | 功能描述:XFRMR PWR 115V 12VAC 1.6A RoHS:是 類別:變壓器 >> 功率 系列:ST 標(biāo)準(zhǔn)包裝:1 系列:260 類型:標(biāo)準(zhǔn) 最大功率:65 VA 主線圈:雙 副線圈:三路，中心抽頭 在某電流時(shí)的串聯(lián)輸出電壓:500 VAC @ 85mA，5 VAC @ 2A，6.3 VAC @ 2A 在某電流時(shí)的并聯(lián)輸出電壓:- 安裝類型:底座安裝 尺寸/尺寸:102.36mm L x 67.31mm W 高度 - 座高（最大）:66.80mm 端接類型:導(dǎo)線引線 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。