參數(shù)資料
型號(hào)： ST52514K1
英文描述： IC MAX 7000 CPLD 128 100-FBGA
中文描述： 8位重癥監(jiān)護(hù)病房，10位ADC。兩個(gè)定時(shí)器/脈寬調(diào)制。 I2C總線。的SPI。脊髓損傷。提供了8K閃存
文件頁(yè)數(shù)： 64/106頁(yè)
文件大?。?/td> 1355K
代理商： ST52514K1
9 INSTRUCTION SET
ST52F501L/F502L supplies 107 (98 + 9 Fuzzy)
instructions that perform computations and control
the device. Computational time required for each
instruction consists of one clock pulse for each
Cycle plus 2 clock pulses for the decoding phase.
Total computation time for each instruction is
reported in Table 9.1
The ALU of ST52F501L/F502L can perform
multiplication
(MULT)
and
division
(DIV).
Multiplication is performed by using 8 bit operands
storing the result in 2 registers (16 bit values), see
Division is performed between a 16 bit dividend
and an 8 bit divider, the result and the remainder
are stored in two 8-bit registers (see Figure 3.4).
9.1 Addressing Modes
ST52F501L/F502L instructions allow the following
addressing modes:
s
Inherent: this instruction type does not require
an operand because the opcode specifies all the
information necessary to carry out the
instruction. Examples: NOP, SCF.
s
Immediate: these instructions have an operand
as a source immediate value. Examples: LDRC,
ADDI.
s
Direct: the operands of these instructions are
specified with the direct addresses. The
operands can refer (according to the opcode) to
addresses belonging to the different addressing
spaces. Example: SUB, LDRE.
s
Indirect: data addresses that are required are
found in the locations specified as operands.
Both source and/or destination operands can be
addressed indirectly. The operands can refer,
(according to the opcode) to addresses
belonging to different addressing spaces.
Examples: LDRR(reg1),(reg2);
LDER mem_addr,(reg1).
s
Bit Direct: operands of these instructions directly
address the bits of the specified Register File
locations. Examples: BSET, BTEST.
9.2 Instruction Types
ST52F501L/F502L
supplies
the
following
instruction types:
s
Load Instructions
s
Arithmetic and Logic Instructions
s
Bitwise instructions
s
Jump Instructions
s
Interrupt Management Instructions
s
Control Instructions
The instructions are listed in Table 9.1
Table 9.1 Instruction Set
Load Instructions
Mnemonic
Instruction
Bytes
Cycles
Z
S
C
BLKSET
BLKSET const
2
(*)
-
GETPG
GETPG regx
2
7
-
LDCE
LDCE confx,memy
3
8/9
-
LDCI
LDCI confx, const
3
7
-
LDCNF
LDCNF regx, conf
3
7
-
LDCR
LDCR confx, regy
3
8
-
LDER
LDER memx, regy
3
10
-
LDER
LDER (regx),(regy)
3
11
-
LDER
LDER (regx), regy
3
10
-
LDER
LDER memx,(regy)
3
11
-
LDFR
LDFR fuzzyx, regy
3
8
-
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