參數(shù)資料
型號(hào)： ST52514K1
英文描述： IC MAX 7000 CPLD 128 100-FBGA
中文描述： 8位重癥監(jiān)護(hù)病房，10位ADC。兩個(gè)定時(shí)器/脈寬調(diào)制。 I2C總線。的SPI。脊髓損傷。提供了8K閃存
文件頁(yè)數(shù)： 51/106頁(yè)
文件大?。?/td> 1355K
代理商： ST52514K1
Internal Oscillator Calibration (OSC_SET)
Option Byte 2 (02h)
Reset Value: 0000 0000 (00h)
Bit 7-6: Not Used
Bit 5-0: OSPAR5-0 Internal Oscillator Parameters
These bits are used in order to calibrate the
precision of the internal oscillator working
at 10 MHz. The six bits enable some
current generators with steps of 0.05
A
corresponding to interval of frequency of
100KHz.
Warning:
the
maximum
configuration
value
allowed for oscillator parameters OSPAR5:0 is
101000 (40). The value corresponding to the 10
MHz by design is 010100 (20).
PLVD & PDR Setup Register (PLVD_SET)
Option Byte 3 (03h)
Reset Value: 0000 0000 (00h)
Bit 7: PDREN Power Down Reset Enable
0: PDR disabled
1: PDR enabled
Bit 6-3: Not Used
Bit 2: PLVDSEL PLVD Action selection
0: PLVD generates a Reset
1: PLVD generates a Interrupt
Bit 1-0: PLVDR1-0 PLVD detection levels for reset
00: PLVD disabled
01: Lowest detection level
10: Medium detection level
11: Highest detection level
Remark: The PLVDR1-0 bits are used only if the
PLVD has been configured to generate a reset
(PVDSEL=0), otherwise the PLVDI1-0 of the
PLVD_CR configuration register are used (see
above)
Wake-Up Time Prescaler (WAKEUP)
Option Byte 7 (07h)
Reset Value: 0000 0000 (00h)
Bit 7-0: WK7-0 Wake-up prescaler
This byte determinates the time delay for
the stabilization of the oscillator after an
External Reset or a POR and after the
wake-up from Halt. The time delay is
computed
according
to
the
following
formula:
Warning: If the internal clock is used as clock
source the prescaler is not used.
6.6.3 Input Registers.
IAP Status Register (IAP_SR)
Input Register 40 (028h) Read only
Reset Value: 0000 0000 (00h)
Bit 7: PLVDST PLVD Status Register
0: Vdd below the current PLVD threshold
1: Vdd above the current PLVD threshold
Bit 6-2: Not used
Bit 1-0: See EEPROM Input Register paragraph
70
-
OSPAR5 OSPAR4 OSPAR3 OSPAR2 OSPAR1 OSPAR0
70
PDREN
-
PLVDSEL PLVDR1 PLVDR0
70
WK7
WK6
WK5
WK4
WK3
WK2
WK1
WK0
70
PLVDST
-
PRTCD
ABRT
Delay
128
WAKEUP
1
+
() Tclk
×
=
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