參數(shù)資料
型號(hào)： ST52514K1
英文描述： IC MAX 7000 CPLD 128 100-FBGA
中文描述： 8位重癥監(jiān)護(hù)病房，10位ADC。兩個(gè)定時(shí)器/脈寬調(diào)制。 I2C總線。的SPI。脊髓損傷。提供了8K閃存
文件頁數(shù)： 29/106頁
文件大?。?/td> 1355K
代理商： ST52514K1
4 MEMORY PROGRAMMING
ST52F501L/F502L
provides
an
on-chip
user
programmable non-volatile memory, which allows
fast and reliable storage of user data.
Program/Data
Memory
addressing
space
is
composed by a Single Voltage Flash Memory and
a RAM memory bench. The ST52F502L devices
also have a Data EEPROM bench to store
permanent data with long term retention and a high
number of write/erase cycles.
All the Program Data memory addresses can
execute code, including RAM and EEPROM
benches.
The memory is programmed by setting the Vpp pin
equal to Vdd. Data and commands are transmitted
through the I2C serial communication protocol. The
same procedure is used to perform “In-Situ” the
programming of the device after it is mounted in
the user system. Data can also be written in run-
time with the In-Application Programming (IAP).
The Memory can be locked by the user during the
programming phase, in order to prevent external
operation such as reading the program code and
assuring protection of user intellectual property.
Flash and EEPROM pages can be protected by
unintentional writings.
Remark: the memory contents are protected by
the Error Correction Code (ECC) algorithm that
uses a 4-bit redundancy to correct one bit errors.
4.1 Program/Data Memory Organization
The Program/Data Memory is organized as
described in Section 2.3. The various sales types
have different amounts of each type of memory.
Table 4.1 describes the memory benches amount
and page allocation for each sales type.
The addressing spaces are organized in pages of
256 bytes. Each page is composed by blocks of 32
bytes. Memory programming is performed one
block at a time in order to speed-up the
programming time (about 2.5 ms per block).
The whole location address is composed as
follows:
15
87
54
0
Page address
Block address address inside the block
Table 4.1 Sales Types Memory Organization
Device
Flash Memory
RAM Memory
EEPROM Memory
Amount
Pages
Amount
Page
Amount
Page
ST52F501Lx1x6
2048 bytes
0 to 7
256 bytes
32
-
ST52F501Lx2x6
4096 bytes
0 to 15
256 bytes
32
-
ST52F501Lx3x6
8192 bytes
0 to 31
256 bytes
32
-
ST52F502Lx1x6
1792 bytes
0 to 6
256 bytes
32
256 bytes
7
ST52F502Lx2x6
3840 bytes
0 to 14
256 bytes
32
256 bytes
15
ST52F502Lx3x6
7936 bytes
0 to 30
256 bytes
32
256 bytes
31
Legend:
c:
Y=16 pins, F=20 pins, G=28 pins, K=32/34 pin
p:
B=DIP, M=SO, T=TQFP
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