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參數(shù)資料
| 型號： | ST52514K1 |
| 英文描述： | IC MAX 7000 CPLD 128 100-FBGA |
| 中文描述： | 8位重癥監(jiān)護病房，10位ADC。兩個定時器/脈寬調(diào)制。 I2C總線。的SPI。脊髓損傷。提供了8K閃存 |
| 文件頁數(shù)： | 45/106頁 |
| 文件大小： | 1355K |
| 代理商： | ST52514K1 |
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6.2 Reset
Six reset sources are available:
s
RESET pin (external source)
s
WATCHDOG (internal source)
s
POWER ON Reset (Internal source)
s
Low Voltage Detector (internal source)
s
Power Down Reset (Internal source)
s
Programmable Halt Wake-up (Internal source)
When a Reset event occurs, the user program
restarts from the beginning.
6.2.1 External Reset. Reset is an input pin. An
internal reset does not affect this pin. A Reset
signal
originated
by
external
sources
is
recognized immediately. The RESET pin may be
used to ensure Vdd has risen to a point where the
ICU can operate correctly before the user program
is run. Reset must be set to Vdd in working mode.
A Pull up resistor of 100 K
guarantees that the
RESET pin is at level “1” when no HALT or Power-
On events occur. If an external resistor is
connected to the RESET pin a minimum value of
10K
must be used.
6.2.2 Power Down Reset (PDR). In
order
to
assure the device has correctly restarted, after the
supply voltage has gone below the working level
(around 1.75 V typical), the PDR supplies an
internal reset of the device. The threshold is fixed
in the range 1.7 V -1.85 V (typical: see electrical
characteristics). An analog spike filtering of around
10
s is considered to avoid unwanted resets.
Figure 6.2 Reset Block Diagram
The PDR works also in Wait and Halt modes,
assuring a continuous monitoring of the device
supply voltage. The PDR can be enabled/disabled
with the Option Byte 3 (PLVD_SET) bit 7.
6.2.3 POR & Reset Procedures.
After the Reset pin is set to Vdd or following a
Power-On Reset event, a Power Down Reset or a
Programmable Halt Wake-up reset (occurred in
Halt mode), the device does not start until the
internal supply voltage has reached the nominal
level of around 1.75 V (typical: see electrical
characteristics) when the PDR releases the reset.
Warning: If the PDR is off, the POR cannot restart.
To make the device restart correctly in this
situation, the supply voltage VDD must drop to 0 V
before restarting the device.
After this level has been
reached, the internal
oscillator (10 MHz) is started and a delay period of
128 Internal clock cycles (12.8
s) is initiated, in
order to allow the oscillator to stabilize and to
ensure that recovery has taken place from the
Reset state.
Then, unless an external quartz clock is configured
to be used, another short count of 4 Internal clock
cycles (400 ns) starts before running the user
program.
Otherwise, if an external quartz clock has been
configured to be used, the Option Byte 7
(WAKEUP) is read and counting starts before
running the user program. The duration of the
counting depends on the contents of the Option
Byte 7 (WAKEUP), that works as a prescaler,
according to the following formula:
POWER-ON
RESET
Vdd
RESET
128 x TCLK
PDR
INTERNAL RESET
WATCHDOG RESET
POW ER DOW N RESET
(W AKEUP+1)
x 128 x TCLK
WATCHDOG
PHW RESET (HALT MODE)
PHW
PROGRAMMABLE LOW VOLTAGE DETECTOR RESET
PLVD
PHW RESET (RUN MODE)
CKMOD1:0
INTERNAL / RC CLOCK
QUARTZ CLOCK
TCLK = Internal Clock period (100 ns)
CKMOD1:0 = see Option Byte 0 (OSC_CR)
W AKEUP = see Option Byte 7 (W AKEUP)
4 x TCLK
Delay
128
WAKEUP
1
+
() Tclk
×
=
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