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參數資料
| 型號： | ST52513K3 |
| 英文描述： | MAX 3000A CPLD 64 MC 100-TQFP |
| 中文描述： | 8位重癥監(jiān)護病房，10位ADC。兩個定時器/脈寬調制。 I2C總線。的SPI。脊髓損傷。提供了8K閃存 |
| 文件頁數： | 53/106頁 |
| 文件大?。?/td> | 1355K |
| 代理商： | ST52513K3 |
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7 FUZZY COMPUTATION (DP)
The ST52F501L/F502L Decision Processor (DP)
main features are:
s
Up to 8 Inputs with 8-bit resolution;
s
1 Kbyte of Program/Data Memory available to
store more than 300 to Membership Functions
(Mbfs) for each Input;
s
Up to 128 Outputs with 8-bit resolution;
s
Possibility of processing fuzzy rules with an
UNLIMITED number of antecedents;
s
UNLIMITED number of Rules and Fuzzy Blocks.
The limits on the number of Fuzzy Rules and
Fuzzy program blocks are only related to the
Program/Data Memory size.
7.1 Fuzzy Inference
The block diagram shown in Figure 7.1 describes
the different steps performed during a Fuzzy
algorithm. The ST52F501L/F502L Core allows for
the implementation of a Mamdami type fuzzy
inference with crisp consequents. Inputs for fuzzy
inference are stored in 8 dedicated Fuzzy input
registers. The LDFR instruction is used to set the
Input Fuzzy registers with values stored in the
Register File. The result of a Fuzzy inference is
stored directly in a location of the Register File.
7.2 Fuzzyfication Phase
In this phase the intersection (alpha weight)
between the input values and the related Mbfs
(Figure 7.2) is performed.
Eight Fuzzy Input registers are available for Fuzzy
inferences.
Figure 7.1 Fuzzy Inference
Figure 7.2 Alpha Weight Calculation
After loading the input values by using the LDFR
assembler instruction, the user can start the fuzzy
inference
by
using
the
FUZZY
assembler
instruction. During fuzzyfication: input data is
transformed in the activation level (alpha weight) of
the Mbf’s.
7.3 Inference Phase
The Inference Phase manages the alpha weights
obtained during the fuzzyfication phase to compute
the truth value (
ω) for each rule.
This is a calculation of the maximum (for the OR
operator) and/or minimum (for the AND operator)
performed on alpha values according to the logical
connectives of Fuzzy Rules.
Several conditions may be linked together by
linguistic connectives AND/OR, NOT operators
and brackets.
The truth value
ω and the related output singleton
are used by the Defuzzyfication phase, in order
to complete the inference calculation.
11
1m
n1
nm
FUZZYFICATION
INFERENCE
PHASE
DEFUZZYFICATION
N rules
N rules -1
2
1
Input Values
Output Values
1
αij
j-th Mbf
i-th INPUT VARIABLE
相關PDF資料 |
PDF描述 |
|---|---|
| ST52513Y2 | MAX 3000A CPLD 256 MC 256-FBGA |
| ST52513Y3 | MAX II CPLD 570 LE 256-FBGA |
| ST52514F1 | MAX II CPLD 570 LE 100-TQFP |
| ST52514F3 | IC MAX 7000 CPLD 128 100-TQFP |
| ST52514G1 | IC MAX 7000 CPLD 32 44-TQFP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ST52513Y2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52513Y3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514F1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514F3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514G1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
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