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| 型號： | ST52513K3 |
| 英文描述： | MAX 3000A CPLD 64 MC 100-TQFP |
| 中文描述： | 8位重癥監(jiān)護病房，10位ADC。兩個定時器/脈寬調(diào)制。 I2C總線。的SPI。脊髓損傷。提供了8K閃存 |
| 文件頁數(shù)： | 25/106頁 |
| 文件大?。?/td> | 1355K |
| 代理商： | ST52513K3 |
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3 INTERNAL ARCHITECTURE
ST52F501L/F502L’s architecture is Register File
based and is composed of the following blocks and
peripherals:
s
Control Unit (CU)
s
Data Processing Unit (DPU)
s
Decision Processor (DP)
s
ALU
s
Memory Interface
s
up to 256 bytes Register File
s
Program/Data Memory
s
Data EEPROM
s
Interrupts Controller
s
Clock Oscillator
s
PLVD, PDR and POR
s
Digital I/O ports
s
Timer/PWM
s
Timer/PWM with IR Driver
s
I2C
s
SPI
s
SCI
s
PHW
Figure 3.1 CU Block Diagram
3.1 Control Unit and Data Processing Unit
The Control Unit (CU) decodes the instructions
stored in the Program Memory and generates the
appropriate control signals. The main parts of the
CU are illustrated in Figure 3.1.
The five different parts of the CU manage Loading,
Logic/Arithmetic, Jump, Control and the Fuzzy
instruction set.
The block called “Collector” manages the signals
deriving from the different parts of the CU. The
collector
defines
the
signals
for
the
Data
Processing Unit (DPU) and Decision Processor
(DP), as well as for the different peripherals of the
ICU.
The block called “Arbiter” manages the different
parts of the CU, so that only one part of the system
is activated during working mode.
The CU structure is extremely flexible and was
designed with the purpose of easily adapting the
core of the microcontroller to market needs. New
instruction sets or new peripherals can easily be
included without changing the structure of the
microcontroller, maintaining code compatibility.
A set of 107 different instructions is available. Each
instruction requires a number of clock pulses to be
performed that depends on the complexity of the
instruction itself. The clock pulses to execute the
instructions are driven directly by the masterclock,
which has the same frequency of the oscillator
signal supplied.
Loading
Instruction Set
Logic Arithmetic
Instruction Set
Jump
Instruction Set
Control
Instruction Set
Decision Processor
Instruction Set
C
O
L
E
C
T
O
R
Control
Signals
A
R
B
I
T
E
R
MicroCode
Clock Master
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST52513Y2 | MAX 3000A CPLD 256 MC 256-FBGA |
| ST52513Y3 | MAX II CPLD 570 LE 256-FBGA |
| ST52514F1 | MAX II CPLD 570 LE 100-TQFP |
| ST52514F3 | IC MAX 7000 CPLD 128 100-TQFP |
| ST52514G1 | IC MAX 7000 CPLD 32 44-TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST52513Y2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52513Y3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514F1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514F3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514G1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
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