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| 型號： | ST52513K3 |
| 英文描述： | MAX 3000A CPLD 64 MC 100-TQFP |
| 中文描述： | 8位重癥監(jiān)護(hù)病房，10位ADC。兩個定時器/脈寬調(diào)制。 I2C總線。的SPI。脊髓損傷。提供了8K閃存 |
| 文件頁數(shù)： | 46/106頁 |
| 文件大?。?/td> | 1355K |
| 代理商： | ST52513K3 |
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This delay has been introduced in order to ensure
that the oscillator has become stable after its
restart, when a quartz clock is used.
If the Reset is generated by the Programmable
Low Voltage Detector or the Watchdog or the PHW
(only in Run mode), the oscillator is not turned off;
for this reason the CPU is then restarted
immediately, without the delay.
After a RESET procedure is completed, the core
reads the instruction stored in the first 3 bytes of
the Program/Data Memory, which contains a
JUMP instruction to the first instruction of the user
program.
The
Assembler
tool
automatically
generates this Jump instruction with the first
instruction address.
6.3 Programmable Low Voltage Detector
The on-chip Programmable Low Voltage Detector
(PLVD) circuit generates an interrupt request or a
reset if the power supply drops below a configured
level. The Reset/Interrupt option can be chosen by
setting bit 2 of Option Byte 3 (PLVD_SET).
If the interrupt option is chosen, the PLVD can be
started choosing a threshold level by means of the
Configuration Register 51 (033h) (PLVD_CR).
Figure 6.3 Reset procedures flow
In this case the PLVD can be enabled/disabled and
the threshold changed in run time. When Vdd
drops below the detection level, the related
interrupt is served if enabled and the PLVD status
bit 0 (PLVDST) in the PLVD_SR Input Register 57
(039h) is set to ‘1’. A new interrupt request cannot
be generated until the Vdd rises up the trigger
level. When the Vdd is above the trigger level the
LVDST bit is ‘0’.
If the Reset option has been set, the PLVD can be
enabled and the threshold can be chosen only at
start-up
by
means
of
the
Option
Byte
3
(PLVD_SET) bit 1:0. When the Vdd goes below the
detection level, the device reset is generated; the
reset is released only after the Vdd rises above the
detection level.
There are three levels with hysteresis for the PLVD
falling voltages (see Electrical Characteristics).
The PLVD circuit will only detect a drop if Vdd
voltage stays below the safe threshold for at least
5
s before activation/deactivation of the PLVD in
order to filter voltage spikes.
Remark: the PLVD function isn’t active when it is
in HALT mode.
Vdd > 1.45
POR_blk=ON ; POR=Vdd => RESET
PDR=ON ; PDD=0 => RESET
Vdd > 1.75
POR_blk=ON ; POR=0 => switches on EEPROM
references and switches on the references for the
PDR and PHW
PDR=ON ; PDD=0 => RESET
Vdd = 0
Vdd < 1
PDR=ON
PDD=1=>POR_blk=OFF ; POR=0
Vdd > 1.75
Vdd > 1
PDR=ON ; PDD=0 => RESET =>
=> POR_blk=ON ; POR=0
Vdd > 1.75
Vdd = 0
y
Legenda
POR_blk = PowerOn block
POR = PowerOn output signal
PDR = PowerDown Reset block
PDD = PowerDown output signal
Rising Vdd slope
Falling Vdd slope
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST52513Y2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52513Y3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514F1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514F3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514G1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
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