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參數(shù)資料
| 型號(hào)： | ST52430K3 |
| 英文描述： | MAX 7000 CPLD 64 MC 84-PLCC |
| 中文描述： | 8位三個(gè)定時(shí)器/脈寬調(diào)制重癥監(jiān)護(hù)病房。 ADC的。脊髓損傷。水分散粒劑。提供了8K存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 43/88頁(yè) |
| 文件大?。?/td> | 1162K |
| 代理商： | ST52430K3 |
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ST52T430/E430
9 WATCHDOG TIMER
9.1 Operational Description
The Watchdog Timer (WDT) is used to detect the
occurrence of a software fault, usually generated
by external interference or by unforeseen logical
conditions, which cause the application program to
abandon its normal sequence. The WDT circuit
generates
an
MCU
reset
on
expiry
of
a
programmed time period, unless the program
refreshes the WDT before the end of the
programmed time delay.
16 different delays can be selected by using the
WDT configuration register.
After the end of the delay programmed by the
configuration register if the WDT is activated (by
using the assembler instruction WDTSFR), it starts
a reset cycle pulling the reset pin low.
Once the WDT has been activated the application
program has to refresh this peripheral (by the
WDTSFR
instruction) at regular intervals during
normal operation in order to prevent an MCU reset.
In order to stop the WDT during user program
execution the instruction WDTSLP has to be used.
Figure 9.1 Watchdog Block Diagram
The working frequency of the WDT (PRES CLK in
the Figure 9.1) is equal to the clock master. The
clock master is divided by 500, obtaining the WDT
CLK signal, which is used to fix the timeout of the
WDT.
According to the WDT configuration register
values, a WDT delay may be defined between 0.1
ms and 937.5 mS when the clock master is 5 MHz.
By changing the clock master frequency the
timeout delay can be calculated according to the
configuration register values REG_CONF 2, as
described in the following section.
Warning: changing the REG_CONF2 value when
the WDT is active, a WDT reset is generated and
the CPU is restarted. To avoid this side effect, use
the WDTSLP instruction before changing the
REG_CONF2.
Table 9.1 Watchdog Timing range (CLK=5
MHz)
WDT timeout period (ms)
min
0.1
max
937.5
D0
D1
D2
D3
REG_CONF 2
RESET
WDTRFR
PRES CLK = CLK MASTER
WDTSLP
PRESCALER
WDT
RESET
GENERATOR
RESET
WTD CLK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST52440F2 | MAX 7000 CPLD 64 MC 100-TQFP |
| ST52440F3 | MAX 7000 CPLD 64 MC 44-TQFP |
| ST52440G2 | MAX 7000 CPLD 64 MC 44-TQFP |
| ST52440G3 | MAX 7000 CPLD 64 MC 44-TQFP |
| ST52501LF1 | MAX 7000 CPLD 128 MC 84-PLCC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST52440F2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH TIMER/PWM. ANALOG COMPARATOR. TRIAC/PWM TIMER. WDG. UP TO 8K EPROM |
| ST52440F3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH TIMER/PWM. ANALOG COMPARATOR. TRIAC/PWM TIMER. WDG. UP TO 8K EPROM |
| ST52440G2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH TIMER/PWM. ANALOG COMPARATOR. TRIAC/PWM TIMER. WDG. UP TO 8K EPROM |
| ST52440G3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH TIMER/PWM. ANALOG COMPARATOR. TRIAC/PWM TIMER. WDG. UP TO 8K EPROM |
| ST5-24B19 | 功能描述:電源變壓器 SPLIT BOBBIN HORZ MOUNT XFMR RoHS:否 制造商:Triad Magnetics 功率額定值:12 VA 初級(jí)電壓額定值:115 V / 230 V 次級(jí)電壓額定值:12 V / 24 V 安裝風(fēng)格:SMD/SMT 一次繞組:Dual Primary Winding 二次繞組:Dual Secondary Winding 長(zhǎng)度:2.5 in 寬度:2 in 高度:1.062 in |
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