參數(shù)資料
型號(hào): ST52430K3
英文描述: MAX 7000 CPLD 64 MC 84-PLCC
中文描述: 8位三個(gè)定時(shí)器/脈寬調(diào)制重癥監(jiān)護(hù)病房。 ADC的。脊髓損傷。水分散粒劑。提供了8K存儲(chǔ)器
文件頁(yè)數(shù): 30/88頁(yè)
文件大小: 1162K
代理商: ST52430K3
ST52T430/E430
Figure 6.2 Port B Functional Blocks
6.3 Output Mode
The output configuration is selected by setting the
corresponding configuration register bit to “0”
(REG_CONF 4, 13 and 15) (see paragraph I/O
Digital data is transferred to the related I/O Port by
means of the Output register via the assembler
instructions LDPE or LDPR.
6.4 Alternate Functions
Several ST52x430 pins are configurable to be
used with different functions (see Table 1.1).
When an on-chip peripheral is configured to use a
pin, the correct I/O mode of the related pin must be
selected.
For example: if pin 26 (PA5/T0CLK in the SO34)
has to be used as an external PWM/Timer0 clock,
the Reg_Conf 4(5) bit must be set to ‘1’.
When the signal is an on-chip peripheral input the
related I/O pin has to be configured in Input Mode.
When a pin is used as an A/D Converter input the
related I/O pin is automatically set in tristate. The
analog
multiplexer
(controlled
by
the
A/D
configuration
Register)
switches
the
analog
voltage present on the selected pin to the common
analog rail, which is connected to the ADC input.
It is recommended that the voltage level not be
changed or that any port pins not be loaded while
conversion
is
running.
Furthermore,
it
is
recommended that clocking pins not be located
close to a selected analog pin.
6.5 I/O Port Configuration Registers
The I/O mode for each bit of the three ports is
selected by using the Configuration Registers 4,
Table 6.2
Input Register and I/O Ports
PORT A
PORT B
PORT C
IR 9
IR 10
IR 11
Table 6.3 Output Register and I/O Ports
PORT A
PORT B
PORT C
OR 0
OR 1
OR 2
TO A/D CONVERTER
CMOS
PORT B PIN
FROM CONFIGURATION REGISTER
TO INPUT REGISTER
FROM OUTPUT REGISTERS
FROM CONFIGURATION REGISTER
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