參數(shù)資料
型號: ST52430K3
英文描述: MAX 7000 CPLD 64 MC 84-PLCC
中文描述: 8位三個定時器/脈寬調(diào)制重癥監(jiān)護病房。 ADC的。脊髓損傷。水分散粒劑。提供了8K存儲器
文件頁數(shù): 41/88頁
文件大?。?/td> 1162K
代理商: ST52430K3
ST52T430/E430
If input voltage is less than VSS (voltage reference
low) then the result is equal to 00h.
The A/D converter is linear and the digital result of
the conversion is provided by the following
formula:
Where Reference Voltage is Vdda - Vss.
The accuracy of the conversion is described in the
Electrical Characteristics Section.
The A/D converter is not affected by the WAIT
mode.
When the MCU enters HALT mode with A/D
converter enabled, the converter is disabled until
HALT mode is terminated and the start-up delay
has elapsed. A stabilization period is also required
before accurate conversions can be performed.
Figure 8.2 Conf. Register (REG_CONF 3)
8.2.1 Operating Modes.
Four main operating modes can be selected by
setting the values of the LP and SEQ bit in the A/D
configuration Register.
One Channel Single Mode
In this mode (SEQ = ‘0’’, LP = ‘0’) the A/D provides
an EOC signal after the end of channel i-th
conversion; then the A/D waits for a new start
event. Channel i-th is identified by the bit CH0,
CH1, CH2.
i.e CH(2:0) = ‘011’ means conversion of channel 3
then stop.
Multiple Channels Single Mode
In this mode (SEQ = ‘1’, LP = ‘0’) the A/D provides
an EOC signal after the end of the channels
sequence conversion identified by the bit CH0,
CH1, CH2; then the A/D waits for a new start event.
i.e. CH(2:0) = ‘011’ means conversion of channels
0,1,2 and 3 then stop.
Digitalr es ult
255inputVoltage
re fe re nce V oltage
------------------------------------------------
=
D 7
D0
CH2 CH1 CH0 SCK SEQ POW
LP STR
REG_CONF 3
START/STOP
CONVERSION MODE SEL.
ON/OFF A/D
CONVERSION MODE SEL.
CLOCK SELECTOR
CHANNELS SEL.
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