- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383837 > ST16C654IJ68 (EXAR CORP) 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO PDF資料下載
參數(shù)資料
| 型號： | ST16C654IJ68 |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO |
| 中文描述： | 4 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 27/51頁 |
| 文件大小： | 968K |
| 代理商： | ST16C654IJ68 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當(dāng)前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁
ST16C654/654D
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
27
]
ISR[0]: Interrupt Status
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source
Table 11
).
ISR[4]: Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match
of the Xoff character(s) or a special character.
ISR[5]: Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-5 indicates that CTS# or RTS# has changed state
from a logic low to logic high.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
4.5
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
T
ABLE
11: I
NTERRUPT
S
OURCE
AND
P
RIORITY
L
EVEL
P
RIORITY
ISR R
EGISTER
S
TATUS
B
ITS
S
OURCE
OF
INTERRUPT
L
EVEL
B
IT
-5
B
IT
-4
B
IT
-3
B
IT
-2
B
IT
-1
B
IT
-0
1
0
0
0
1
1
0
LSR (Receiver Line Status Register)
2
0
0
1
1
0
0
RXRDY (Receive Data Time-out)
3
0
0
0
1
0
0
RXRDY (Received Data Ready)
4
0
0
0
0
1
0
TXRDY (Transmit Ready)
5
0
0
0
0
0
0
MSR (Modem Status Register)
6
0
1
0
0
0
0
RXRDY (Received Xoff or Special character)
7
1
0
0
0
0
0
CTS#, RTS# change of state
-
0
0
0
0
0
1
None (default)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST16C654IQ100 | 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO |
| ST16C654IQ64 | 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO |
| ST16KF74 | Microcontroller |
| ST16LF74 | Microcontroller |
| ST16MF74 | Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST16C654IJ68-F | 功能描述:UART 接口集成電路 QUAD UARTW/64BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C654IJ68-F | 制造商:Exar Corporation 功能描述:IC QUAD UART 1.5MBPS 5.5V 68-PLCC |
| ST16C654IJ68TR-F | 制造商:Exar Corporation 功能描述:UART 4-CH 64Byte FIFO 3.3V/5V 68-Pin PLCC T/R 制造商:Exar Corporation 功能描述:2.97V to 5.5V Quad UART with 64 Byte FIFOs PLCC 68 制造商:Exar Corporation 功能描述:ST16C654IJ68TR-F |
| ST16C654IQ | 制造商:Exar Corporation 功能描述: |
| ST16C654IQ100 | 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD UART WITH 64-BYTE FIFO AND INFRARED (IrDA) ENCODER/DECODER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。