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參數(shù)資料
| 型號： | ST16C654IJ68 |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO |
| 中文描述： | 4 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 13/51頁 |
| 文件大小： | 968K |
| 代理商： | ST16C654IJ68 |
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ST16C654/654D
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
13
Table 6 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X sampling
rate. When using a non-standard frequency crystal or external clock, the divisor value can be calculated for
DLL/DLM with the following equation.
2.9
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal clock.
A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits, inserts the
proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in the Line
Status Register (LSR bit-5 and bit-6).
2.9.1
Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
Transmitter
F
IGURE
6. B
AUD
R
ATE
G
ENERATOR
AND
P
RESCALER
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16)
T
ABLE
6: T
YPICAL
DATA
RATES
WITH
A
14.7456 MH
Z
CRYSTAL
OR
EXTERNAL
CLOCK
O
UTPUT
Data Rate
MCR Bit-7=1
O
UTPUT
Data Rate
MCR Bit-7=0
(D
EFAULT
)
D
IVISOR
FOR
16x
Clock (Decimal)
D
IVISOR
FOR
16x
Clock (HEX)
DLM
P
ROGRAM
V
ALUE
(HEX)
DLL
P
ROGRAM
V
ALUE
(HEX)
D
ATA
R
ATE
E
RROR
(%)
100
600
1200
2400
4800
9600
19.2k
38.4k
57.6k
115.2k
230.4k
400
2400
4800
9600
19.2k
38.4k
76.8k
153.6k
230.4k
460.8k
921.6k
2304
384
192
96
48
24
12
6
4
2
1
900
180
C0
60
30
18
0C
06
04
02
01
09
01
00
00
00
00
00
00
00
00
00
00
80
C0
60
30
18
0C
06
04
02
01
0
0
0
0
0
0
0
0
0
0
0
XTAL1
XTAL2
Crystal
Osc/
Buffer
MCR Bit-7=0
(default)
MCR Bit-7=1
DLL and DLM
Registers
Prescaler
Divide by 1
Prescaler
Divide by 4
16X
Sam pling
Rate Clock to
Transmitter
Baud Rate
Generator
Logic
相關(guān)PDF資料 |
PDF描述 |
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| ST16C654IQ100 | 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO |
| ST16C654IQ64 | 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO |
| ST16KF74 | Microcontroller |
| ST16LF74 | Microcontroller |
| ST16MF74 | Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST16C654IJ68-F | 功能描述:UART 接口集成電路 QUAD UARTW/64BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C654IJ68-F | 制造商:Exar Corporation 功能描述:IC QUAD UART 1.5MBPS 5.5V 68-PLCC |
| ST16C654IJ68TR-F | 制造商:Exar Corporation 功能描述:UART 4-CH 64Byte FIFO 3.3V/5V 68-Pin PLCC T/R 制造商:Exar Corporation 功能描述:2.97V to 5.5V Quad UART with 64 Byte FIFOs PLCC 68 制造商:Exar Corporation 功能描述:ST16C654IJ68TR-F |
| ST16C654IQ | 制造商:Exar Corporation 功能描述: |
| ST16C654IQ100 | 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD UART WITH 64-BYTE FIFO AND INFRARED (IrDA) ENCODER/DECODER |
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