參數(shù)資料
型號: ST16C654CJ68
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
中文描述: 4 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 49/51頁
文件大小: 968K
代理商: ST16C654CJ68
ST16C654/654D
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
49
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order
to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of
any circuits described herein, conveys no license under any patent or other right, and makes no
representation that the circuits are free of patent infringement. Charts and schedules contained here in are
only for illustration purposes and may vary depending upon a user’s specific application. While the
information in this publication has been carefully checked; no responsibility, however, is assumed for
inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where
the failure or malfunction of the product can reasonably be expected to cause failure of the life support
system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of
injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR
Corporation is adequately protected under the circumstances.
Copyright 2003 EXAR Corporation
Datasheet October 2003.
Send your UART technical inquiry with technical details to hotline:
uarttechsupport@exar.com
.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
REVISION HISTORY
D
ATE
R
EVISION
D
ESCRIPTION
October 2003
Rev 5.00
Changed to standard style single-column format. Text descriptions were
clarified and simplified (eg. DMA operation, FIFO mode vs. Non-FIFO
mode operations etc). Clarified timing diagrams. Renamed Rclk
(Receive Clock) to Bclk (Baud Clock) and timing symbols. Added T
CS
,
T
RWS
and T
RST
.Renamed FIFORdy register to FSTAT register.
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