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參數(shù)資料
| 型號： | ST16C654CJ68 |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO |
| 中文描述： | 4 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 28/51頁 |
| 文件大?。?/td> | 968K |
| 代理商： | ST16C654CJ68 |
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ST16C654/654D
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
28
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No receive FIFO reset (default)
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
Controls the behavior of the -TXRDY and -RXRDY pins. See DMA operation section for details.
Logic 0 = Normal Operation (default).
Logic 1 = DMA Mode.
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = one)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load.
Table 12
below shows the selections. EFR bit-4
must be set to ‘1’ before these bits can be accessed. Note that the receiver and the transmitter cannot use
different trigger tables. Whichever selection is made last applies to both the RX and TX side.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level.
Table 12
shows the complete selections.
T
ABLE
12: T
RANSMIT
AND
R
ECEIVE
FIFO T
RIGGER
L
EVEL
S
ELECTION
FCR
B
IT
-7
FCR
B
IT
-6
FCR
B
IT
-5
FCR
BIT
-4
R
ECEIVE
T
RIGGER
L
EVEL
T
RANSMIT
T
RIGGER
L
EVEL
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
8
16
56
60
8
16
32
56
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST16C654CQ100 | 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO |
| ST16C654 | Linear Voltage Regulator IC; Output Current Max:350mA; Supply Voltage Max:6V; Package/Case:8-TSSOP; Output Current:600mA; Output Voltage:5V; Current Rating:30.05A; Leaded Process Compatible:No; Output Voltage Max:5V |
| ST16C654CQ64 | 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO |
| ST16C654D | Voltage Regulator IC; Package/Case:8-MSOP; Output Current:300mA; Output Voltage:3.3V; Supply Voltage Max:6V; Current Rating:300mA; Leaded Process Compatible:No; Output Current Max:300mA; Output Voltage Max:3.3V RoHS Compliant: No |
| ST16C654DIQ64 | 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST16C654CJ68-F | 功能描述:UART 接口集成電路 2.97V-5.5V 64B FIFO temp 0C to 70C; UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C654CJ68-F DRY PACKED | 制造商:EXAR 功能描述:UART 4-CH 64Byte FIFO 3.3V/5V 68-Pin PLCC |
| ST16C654CJ68TR | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| ST16C654CJ68TR-F | 功能描述:UART 接口集成電路 QUAD UARTW/64BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C654CQ100 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
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