參數(shù)資料
型號(hào)： SSTU32865
廠商： NXP Semiconductors N.V.
英文描述： 1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM
中文描述： 1.8伏28位1:2登記緩沖區(qū)的DDR2 RDIMM特別平價(jià)
文件頁(yè)數(shù)： 9/29頁(yè)
文件大?。?/td> 157K
代理商： SSTU32865
9397 750 13799
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 28 September 2004
9 of 29
Philips Semiconductors
SSTU32865
1.8 V DDR registered buffer with parity
[2]
This condition assumes PTYERR is HIGH at the crossing of CK going HIGH and CK going LOW. If PTYERR is LOW, it stays latched
LOW for two clock cycles or until RESET is driven LOW.
CSGATEEN is ‘don’t care’ for PTYERR.
[3]
PTYERR
0
is the previous state of output PTYERR.
7.2 Functional information
This 28-bit 1:2 registered buffer with parity is designed for 1.7 V to 1.9 V V
DD
operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The
control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized
to drive the DDR2 DIMM load.
The SSTU32865 operates from a differential clock (CK and CK). Data are registered at
the crossing of CK going HIGH, and CK going LOW.
The device supports low-power standby operation. When the reset input (RESET) is LOW,
the differential input receivers are disabled, and undriven (floating) data, clock and
reference voltage (V
REF
) inputs are allowed. In addition, when RESET is LOW all registers
are reset, and all outputs except PTYERR are forced LOW. The LVCMOS RESET input
must always be held at a valid logic HIGH or LOW level.
To ensure defined outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with
respect to CK and CK. Therefore, no timing relationship can be guaranteed between the
two. When entering reset, the register will be cleared and the data outputs will be driven
LOW quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable
the differential input receivers. As long as the data inputs are LOW, and the clock is stable
during the time from the LOW-to-HIGH transition of RESET until the input receivers are
fully enabled, the design of the SSTU32865 ensures that the outputs remain LOW, thus
ensuring no glitches on the output.
The device monitors both DCS0 and DCS1 inputs and will gate the Qn outputs from
changing states when both DCS0 and DCS1 are HIGH. If either DCS0 or DCS1 input is
LOW, the Qn outputs will function normally. The RESET input has priority over the DCS0
and DCS1 control and will force the Qn outputs LOW and the PTYERR output HIGH. If the
DCSn-control functionality is not desired, then the CSGATEEN input can be hardwired to
ground, in which case, the setup-time requirement for DCSn would be the same as for the
other Dn data inputs.
The SSTU32865 includes a parity checking function. The SSTU32865 accepts a parity bit
from the memory controller at its input pin PARIN, compares it with the data received on
the Dn inputs (with either DCS0 or DCS1 active) and indicates whether a parity error has
occurred on its open-drain PTYERR pin (active LOW).
相關(guān)PDF資料
PDF描述
SSTU32865EG Linear Voltage Regulator IC; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No
SSTUA32864 Linear Voltage Regulator IC; Package/Case:8-MSOP; Current Rating:250mA; Leaded Process Compatible:No; Output Voltage Max:1.8V; Peak Reflow Compatible (260 C):No; Reel Quantity:2500; Voltage Regulator Type:Low Dropout (LDO)
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SSTUA32864EG Linear Voltage Regulator IC; Package/Case:8-MSOP; Current Rating:250mA; Leaded Process Compatible:No; Output Voltage Max:2.8V; Peak Reflow Compatible (260 C):No; Reel Quantity:2500; Voltage Regulator Type:Low Dropout (LDO)
SSTVN16859 13-bit 1:2 SSTL_2 registered buffer for DDR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SSTU32865EG 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM
SSTU32865ET 功能描述:寄存器 1.8V 28-BIT REG BUF/PARITY RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTU32865ET,518 功能描述:寄存器 1.8V 28-BIT REG RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTU32865ET,551 功能描述:寄存器 1.8V 28-BIT REG RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTU32865ET,557 功能描述:寄存器 1.8V 28-BIT REG RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
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