參數(shù)資料
型號(hào)： SSTU32865
廠商： NXP Semiconductors N.V.
英文描述： 1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM
中文描述： 1.8伏28位1:2登記緩沖區(qū)的DDR2 RDIMM特別平價(jià)
文件頁(yè)數(shù)： 1/29頁(yè)
文件大小： 157K
代理商： SSTU32865
1.
General description
The SSTU32865 is a 1.8 V 28-bit 1:2 register specifically designed for use on two rank by
four (2R
×
4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is
similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the
functionality of the normally required two registers in a single package, thereby freeing up
board real-estate and facilitating routing to accommodate high-density Dual In-line
Memory Module (DIMM) designs.
The SSTU32865 also integrates a parity function, which accepts a parity bit from the
memory controller, compares it with the data received on the D-inputs and indicates
whether a parity error has occurred on its open-drain PTYERR pin (active-LOW).
The SSTU32865 is packaged in a 160-ball, 12
×
18 grid, 0.65 mm ball pitch, thin profile
fine-pitch ball grid array (TFBGA) package, which—while requiring a minimum
9 mm
×
13 mm of board space—allows for adequate signal routing and escape using
conventional card technology.
2.
Features
I
28-bit data register supporting DDR2
I
Fully compliant to JEDEC standard JESD82-9
I
Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two
JEDEC-standard DDR2 registers (i.e. 2
×
SSTU32864 or 2
×
SSTU32866)
I
Parity checking function across 22 input data bits
I
Parity out signal
I
Controlled output impedance drivers enable optimal signal integrity and speed
I
Exceeds JESD82-9 speed performance (1.8 ns max. single-bit switching propagation
delay, 2.0 ns max. mass-switching)
I
Supports up to 450 MHz clock frequency of operation
I
Optimized pinout for high-density DDR2 module design
I
Chip-selects minimize power consumption by gating data outputs from changing state
I
Supports Stub Series Terminated Logic SSTL_18 data inputs
I
Differential clock (CK and CK) inputs
I
Supports Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)
switching levels on the control and RESET inputs
I
Single 1.8 V supply operation
I
Available in 160-ball 9 mm
×
13 mm, 0.65 mm ball pitch TFBGA package
SSTU32865
1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM
applications
Rev. 02 — 28 September 2004
Product data sheet
相關(guān)PDF資料
PDF描述
SSTU32865EG Linear Voltage Regulator IC; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No
SSTUA32864 Linear Voltage Regulator IC; Package/Case:8-MSOP; Current Rating:250mA; Leaded Process Compatible:No; Output Voltage Max:1.8V; Peak Reflow Compatible (260 C):No; Reel Quantity:2500; Voltage Regulator Type:Low Dropout (LDO)
SSTUA32864EC Linear Voltage Regulator IC; Package/Case:8-MSOP; Current Rating:250mA; Leaded Process Compatible:No; Output Voltage Max:2.5V; Peak Reflow Compatible (260 C):No; Reel Quantity:2500; Voltage Regulator Type:Low Dropout (LDO)
SSTUA32864EG Linear Voltage Regulator IC; Package/Case:8-MSOP; Current Rating:250mA; Leaded Process Compatible:No; Output Voltage Max:2.8V; Peak Reflow Compatible (260 C):No; Reel Quantity:2500; Voltage Regulator Type:Low Dropout (LDO)
SSTVN16859 13-bit 1:2 SSTL_2 registered buffer for DDR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SSTU32865EG 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM
SSTU32865ET 功能描述:寄存器 1.8V 28-BIT REG BUF/PARITY RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTU32865ET,518 功能描述:寄存器 1.8V 28-BIT REG RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTU32865ET,551 功能描述:寄存器 1.8V 28-BIT REG RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTU32865ET,557 功能描述:寄存器 1.8V 28-BIT REG RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
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