參數(shù)資料
型號: SPAK302PV16VC
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-144
文件頁數(shù): 102/128頁
文件大?。?/td> 641K
代理商: SPAK302PV16VC
Signal Descriptions
5-8
MC68EN302 REFERENCE MANUAL
MOTOROLA
5.4.7 A0
A new signal, A0 has been added for supporting dynamic bus sizing. This signal replaces
the MC68302 A0 that was multiplexed onto UDS. A0 is bidirectional.
The A0 signal appears on the pin if the PM6 bit of the MBCTRL = 0. If PM6= 1 then the pin
is used as TOUT1/PB4.
5.4.8 WEL- Write Enable for Byte 1 (Bit 7–Bit 0)
If the PM7 bit of the MBCTRL = 1, then the active low signal WEL is enabled. If PM7 = 0,
then the pin is used for DREQ/PA13 and is bidirectional.
5.4.9 WEH - Write Enable for Byte 0 (Bit 15–Bit 8)
If the PM8 bit of the MBCTRL = 1, the active low WEH signal appears on the pin. If PM8 =
0, then the pin is used for DACK/PA14 and is bidirectional.
5.4.10 OE - Output Enable
Output - asserted low, pin is bidirectional.
If the PM9 bit of the MBCTRL = 0, the active low OE signal is enabled. If PM9 = 1 then the
pin is used for DONE/PA15 and may be bidirectional.
5.5 MC68EN302 ONLY PIN/SIGNALS
TENA
TX
TCLK
RENA
RX
RCLK
CLSN
PARITY0/DISCPU
PARITY1/BUSW
PARITYE/THREES
TMS
TCK
TRST
TDO
TDI
GND
5.5.1 GND
For proper implementation of the EN302, this pin must be tied to ground.
5.5.2 TRST - JTAG Reset Signal
For normal operation the asynchronous TRST signal must be held low during system reset.
This pin has an internal pullup resistor.
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