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| 型號： | SPAK302PV16VC |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-144 |
| 文件頁數(shù)： | 101/128頁 |
| 文件大小： | 641K |
| 代理商： | SPAK302PV16VC |
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Signal Descriptions
MOTOROLA
MC68EN302 REFERENCE MANUAL
5-7
5.4.1 AMUX - DRAM Address Mux
The AMUX pin is an output only pin provided for implementing external address muxing
circuitry when accessing DRAM. The user may require use of this signal if external masters
are utilizing the EN302 DRAM controller. When performing an access to the EN302 as a
slave, the address is driven as an input, preventing the EN302 DRAM controller from driving
the address bus. Because of this, external muxing must take place. The AMUX pin is also
useful in implementations where a linear DRAM space is required.
The AMUX signal appears on the pin if the PM0 bit of the MBCTRL = 0. If PM0 = 1 then the
pin becomes BRG1 instead.
5.4.2 RAS0 - DRAM Row Address Select, Bit Zero
When the PM1 bit of the MBCTRL = 0, this active low output signal is used to select one of
two banks of DRAM as determined by the DRAM Base Address Register 0 (DBA0).
If PM1 = 1 then the pin becomes BRG2/SDS2/PA7 and is bidirectional depending on the
function chosen
5.4.3 RAS1 - DRAM Row Address Select Bit 1
When the PM2 bit of the MBCTRL = 0, this active low output signal is used to select one of
two banks of DRAM as determined by the DRAM Base Address Register1 (DBA1) CSR.
If PM2 = 1, then the pin is used as BRG3/PA12 and may be bidirectional
5.4.4 CAS0 - DRAM Column Address Select Bit 0
If the PM3 bit of the MBCTRL = 0, this active low output signal is used to enable the DRAM
module upper byte (bits 15–8).
If PM3 = 1 then the pin is used for PB0/IACK7 and may be bidirectional.
5.4.5 CAS1- DRAM Column Address Select Bit 1
If the PM4 bit of the MBCTRL = 0, this active low output signal is used to enable the lower
byte (bits 7–0) of the DRAM module.
If PM4 = 1 then the pin is used for PB1/IACK6 and may be bidirectional.
5.4.6 DRAMRW- DRAM Read/Write
If the PM5 bit of the MBCTRL = 0, this pin is asserted low for a DRAM write cycle. It is
separate from the processor bus R/W signal to allow precharge to take place without regard
to the state of R/W.
If PM5 = 1 then the pin is used for PB2/IACK1 and may be bidirectional.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SPAK56854FG120 | 制造商:Freescale Semiconductor 功能描述: |
| SPAK56857BU120 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:120 MIPS Hybrid Processor |
| SPAK56F803BU80 | 制造商:Freescale Semiconductor 功能描述: |
| SPAK56F805FV80 | 制造商:Freescale Semiconductor 功能描述: |
| SPAKDSP303AG100 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC SPAKDSP303AG100 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
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