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參數(shù)資料
| 型號： | SP973T8CDP |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDIP18 |
| 封裝： | PLASTIC, DP-18 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 293K |
| 代理商： | SP973T8CDP |
SP973T8
6
Circuit Board Construction (Fig.8)
Excellent performance can be obtained from this ADC
using only one solid ground plan for both analog and digital
signals.
With all flash ADCs it is important to restrict digital
crosstalk into the input, not only within the wanted signal
bandwidth but also at frequencies between Nyquist and clock,
as such signals will be aliased down into the wanted signal
bandwidth.
We can give the designer two useful suggestions to reduce
the above. First, due to the on-chip clock regeneration circuit,
a low level clock can be fed to the ADC 1V p-p is
recommended. The second suggestion is the addition of a
small bead inductor in series with and close to the device
analog input.
Supply line decoupling is very important when dealing with
a mix of analog and digital signals as they can provide a source
of digital feedback from the digital output currents. It is wise,
therefore, to decouple the SP973T8 close to the device supply
pins with good quality, high frequency, low inductance
capacitors.
Due to the high clock rates involved, long clock lines to the
device should be avoided to reduce the noise pick up.
Fig.8 Test/application circuit
S
P
9
7
3
T
8
18
10
1
17
2
16
3
15
4
14
5
13
6
12
7
11
8
9
50
0.1
10n
0.1
10n
10nF
MID REF VRM
NOTE: DECOUPLE CLOSE TO PINS
+VE REF VRT
DVCC
DGND
ANALOG INPUT
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
DATA OUTPUTS
(TTL/CMOS
COMPATIBLE)
CLOCK
-VE REF VRB
AVCC
AGND
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