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參數(shù)資料
| 型號： | SP973T8CDP |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDIP18 |
| 封裝： | PLASTIC, DP-18 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 293K |
| 代理商： | SP973T8CDP |
SP973T8
3
ELECTRICAL CHARACTERISTICS DEFINITIONS
Analog Bandwidth
The analog input frequency at which the spectral power of
the fundamental frequency, as determined by Fast Fourier
Transform analysis is 3dB down on the DC level.
Aperture Delay
The delay between the falling edge of the CLOCK signal
and the instant at which the analog input is sampled.
Bit Error Rate (BER)
The number of spurious code errors produced for any
given input sinewave frequency. In this case it is the number
of codes occuring outside the histogram cusp for a 3/
4 F.S.
sinewave.
Differential Non-Linearity (DNL)
The deviation of any code width from an ideal 1LSB step.
Effective Number of Bits (ENOB)
This is a measure of the dynamic performance and is
calculated from the following expression.
ENOB = SNR-1.76
6.02
SNR is the signal-to-noise ratio, in decibels, at the test
frequency.
Integral Non-Linearity (INL)
The deviation of the centre of each code from a reference
line which has been determined by a least squares curve fit.
Output Data Delay
The delay between the 50% point of the falling edge of the
clock signal and the 50% point of any data output change.
Reference Ladder Offset
The voltage error at the ends of the resistor chain caused
by the lead frame and bond wire.
Signal-to-Noise Ratio (SNR)
The ratio of the RMS signal amplitude to the RMS value of
'noise' which is defined as the sum of all other spectral
components including harmonics but excluding DC with a full
scale analog input signal.
Test Levels
Level 1 - 100% production tested
Level 2 - 100% production tested at 25
°C and sample
tested at specified temperatures
Level 3 - Sample tested only
Level 4 - Parameter is guaranteed by design and
characteristics testing
Level 5 - Parameter is a typical value only
Description
Output data bits 3, 2, 1, 0
Clock input pin
Clock threshold level pin
Bottom of reference resistor chain
Function
D3, D2, D1, D0
CLK
VRB
AVCC
AGND
VRM
VIN
VRT
DVCC
DGND
D7
D6, D5, D4
Pin No.
1, 2, 3, 4
5
6
7
8
9
10
11
12
13
14
15
16, 17, 18
5 Volt power to all circuitry except the TTL output
Middle of reference resistor chain
Analog input voltage pin
Top of reference resistor chain
5 Volt power supply to the TTL output stage
Most significant bit (output data bit 7)
Output data bits 6, 5, 4
THERMAL CHARACTERISTICS
DP
Thermal resistance, chip-to-case
θjc
20
°C/W
Thermal resistance, chip-to-ambient
θjA
75
°C/W
RECOMMENDED OPERATING CONDITIONS
Supply Voltage VCC
+5.0V
Reference VRT
+4.3V
Reference VRB
+2.3V
AVCC to DVCC
0mV
AGND to DGND
0mV
Analog Input VIN
2 Vp-p max
PIN DESCRIPTIONS
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