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參數(shù)資料
| 型號： | SP973T8CDP |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDIP18 |
| 封裝： | PLASTIC, DP-18 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 293K |
| 代理商： | SP973T8CDP |
SP973T8
4
APPLICATION NOTES
Analog Input Pin (Fig.3)
The analog input of the SP973T8 is connected to 256
comparators which have a combined capacitance of about
30pF. The sample/latch operation of the comparators causes
the input capacitance to vary slightly as the comparator input
transistors turn on/off. For this reason the input driver circuit
should provide a low impedance signal to keep the harmonic
distortion levels of the driver to a minimum.
The maximum amplitude of the analog input is defined by
the setting of the two reference voltages VRT and VRB. Opti-
mum performance will be obtained with the input signal biased
midway between VRT and VRB with a peak to peak amplitude
of VRT-VRB. The SP973T8 has excellent overload tracking of
input signals with amplitudes greater than VRT-VRB, and will
not be damaged if the absolute maximum ratings are adhered
to.
Voltage Reference Pins (Fig.4)
The SP973T8 converts analog signals in the range
VRB<VIN<VRT into digital format, where VRB produces code 0
and VRT produces code 255. Between the pins VRT and VRB
are a series of 256 resistors forming a reference chain with a
total resistance of 425
(typically). The centre point of the
reference chain is also connected to an external pin named
VRM by which it is possible to provide precision trimming of the
integral linearity of the device.
The maximum value of VRT is VCC-0.7 volts since values
above this figure will start to saturate the comparator, resulting
in noticeable distortion. Optimum performance from a +5 Volt
power supply is obtained with VRT<+4.3V and VRB a further 2
volts below VRT. In addition the VRT, VRB and VRM pins should
be decoupled to ground close to the device pins using good
quality 10nf capacitors. A simple method for providing the
reference voltages is shown in Fig.4, and further information
may be found in applications note AN72. With a reference
ladder voltage of less than 2V the reduced LSB size causes a
larger differential linearity error. Operation of the device below
1.5V may therefore cause missing codes.
Fig.3 One of 255 analog inputs connected to pin 11
ANALOG
INPUT
REF
CHAIN
200A
VRB
VRT
1.5
AVCC
+5V
DGND
DATA OUTPUT
50
+5V
DVCC
Fig,5 TTL output stage
TTL/CMOS Outputs (Fig.5)
The data output levels of the SP973T8 are TTL/CMOS
compatible and switch from 0V to +4V. The output circuit is
capable of operation at clock frequencies in excess of 60MHz
when driving into a standard LSTTL load.
ADC
INTERNAL
RESISTOR
CHAIN
ADC PIN 7
ADC PIN 12
2.45V
ZN458
PRECISION
REFERENCE
4.3V
5V
18k
1.5k
CLAMP LEVEL
FOR VIDEO
APPLICATIONS
Fig.4 Simple reference voltage generation
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