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參數(shù)資料
| 型號(hào)： | SP8605 |
| 元件分類： | 串行ADC |
| 英文描述： | 12-Bit Sampling A/D Converters |
| 中文描述： | 12位采樣的A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 205K |
| 代理商： | SP8605 |
86
To avoid introducing distortion, the source resistance
must be very low, or constant with signal level. The
output impedance provided by most op amps is ideal.
Pins 26 Digital Supply Voltage (V
) and 27 Analog
Supply Voltage (V
) are brought out to separate pins
to maximize accuracy on the chip. They should be
connected together as close as possible to the unit. Pin
27 may be slightly more sensitive than pin 26 to supply
variations, but to maintain maximum system accu-
racy, both should be well–isolated from digital sup-
plies with wide load variations.
To limit the effects of digital switching elsewhere in a
system on the analog performance of the system, it
often makes sense to run a separate +5V supply
conductor from the supply regulator to any analog
components requiring +5V, including the
SP86XX
Series.
If the
SP86XX Series
traces cannot be
separated back to the power supply terminals, and
therefore share the same trace as the logic supply
currents, then a 10 Ohm isolating resistor should be
used between the board supply and pin 24 (V
) and
its bypass capacitors to keep V
glitch–free. The V
S
pins (26 and 27) should be connected together and
bypassed with a parallel combination of a 6.8
μ
F
Tantalum capacitor and a 0.1
μ
F ceramic capacitor
located close to the converter to obtain noise-free
operation. (See
Figure 1
). Noise on the power supply
lines can degrade converter performance, especially
noise and spikes from a switching power supply.
Appropriate supplies or filters must be used.
The GND pins (5 and 16) are also separated internally,
and should be directly connected to a ground plane
under the converter. A ground plane is usually the best
solution for preserving dynamic performance and
reducing noise coupling into sensitive converter cir-
cuits. Where any compromises must be made, the
common return of the analog input signal should be
referenced to pin 5, AGND, on the
SP86XX Series,
which prevents any voltage drops that might occur in
the power supply common returns from appearing in
series with the input signal.
Coupling between analog input and digital lines should
be minimized by careful layout. For instance, if the
lines must cross, they should do so at right angles.
Parallel analog and digital lines should be separated
from each other by a pattern connected to common.
If external full scale and offset potentiometers are
used, the potentiometers and related resistors should
be located as close to the
SP86XX Series
as possible.
“Hot Socket” Precaution
Two separate +5V V
pins, 26 and 27, are used to
minimize noise caused by digital transients. If one pin
is powered and the other is not, the
SP86XX Series
may draw excessive current. In normal operation, this
is not a problem because both pins will be soldered
together. However, during evaluation, incoming in-
spection, repair, etc., where the potential of a “Hot
Socket” exists, care should be taken to apply power to
Figure 4. Acquisition and Conversion Timing
R/C
BUSY
CMode
Acquisition
Conversion
Acquisition
Conversion
t
AP
Hold Time
t
C
t
DBC
t
B
SYMBOL/PARAMETER
t
DBC
BUSY delay from R/C
t
B
BUSY Low
MIN.
TYP.
80
2.5
4.5
9.5
13
150
2.47
4.47
9.47
MAX.
150
2.7
4.7
9.7
UNITS
ns
μ
s
μ
s
μ
s
ns
SP8603
SP8605
SP8610
t
AP
t
AP
t
C
Aperture Delay
Aperture Jitter
Conversion Time
ps, rms
2.70
4.70
9.70
μ
s
μ
s
μ
s
SP8603
SP8605
SP8610
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