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參數(shù)資料
| 型號(hào)： | SP8605 |
| 元件分類： | 串行ADC |
| 英文描述： | 12-Bit Sampling A/D Converters |
| 中文描述： | 12位采樣的A / D轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 10/11頁(yè) |
| 文件大?。?/td> | 205K |
| 代理商： | SP8605 |
88
SYMBOL/PARAMETER
MIN .
TYP.
MAX.
UNITS
t
W
t
DBC
t
B
t
AP
t
AP
t
C
t
DBE
t
DB
t
A
t
A
+ t
C
R/C Pulse Width
BUSY delay from R/C
BUSY LOW
Aperture Delay
Aperture Jitter
Conversion Time
BUSY from End of Conversion
BUSY Delay after Data Valid
Acquisition Time
Throughput Time
SP8603
SP8605
SP8610
Valid Data Held After R/C LOW
CS or HBE LOW before R/C Falls
CS or HBE LOW after R/C Falls
Data Valid from CS LOW, R/C HIGH, and HBE
in Desired State (Load = 100pF)
Delay to Hi-Z State after R/C Falls or
CS Rises (3K
Pullup or Pulldown
All parameters Guaranteed By Design.
40
ns
ns
μ
s
ns
80
2.47
13
150
2.5
100
75
130
150
2.7
ps, rms
2.70
μ
s
ns
ns
ns
25
200
300
3.0
5.0
10.0
20
25
25
μ
s
μ
s
μ
s
ns
ns
ns
ns
t
HDR
t
S
t
H
t
DD
50
5
0
65
150
t
HL
50
150
ns
AC DYNAMIC TIMING DATA
layout of the circuit in front of the
SP86XX Series.
Finally, in multiplexed systems, the timing relative to
when the multiplexer is switched may affect the
analog performance of the system. In most applica-
tions, the multiplexer can be switched as soon as R/C
goes LOW (with appropriate delays), but this may
affect the conversion if the switched signal shows
glitches or significant ringing at the
SP86XX Series
input. Whenever possible, it is safer to wait until the
conversion is completed before switching and multi-
plexer. The extremely fast acquisition time and con-
version time of the
SP86XX Series
make this practi-
cal in many applications.
R/C, it makes sense to keep the rising edge of the
convert pulse outside the time when bit decisions are
being made. In other words, the convert pulse should
either be short (under 100ns so that it transitions before
the MSB decision), or relatively long (i.e., for the
SP8603
, over 2.75
μ
s to transition after the LSB
decision).
Next, although the data outputs are forced into a Hi-Z
state during conversion, fast bus transients can still be
capacitively coupled into the
SP86XX Series.
If the
data bus experiences fast transients during conver-
sion, these transients can be attenuated by adding a
logic buffer to the data outputs. The BUSY output can
be used to enable the buffer.
Naturally, transients on the analog input signal are to
be avoided, especially at times within
±
20ns of R/C
going LOW, when they may be trapped as part of the
charge on the capacitor array. This requires careful
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