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參數(shù)資料
| 型號： | SN54ALVTH16601WD |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS |
| 中文描述： | 2.5-V/3.3-V 18位通用總線收發(fā)器和三態(tài)輸出 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 196K |
| 代理商： | SN54ALVTH16601WD |
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JULY 1999
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, V
CC
= 2.5 V
±
0.2 V
(unless otherwise noted) (see Figure 1)
SN54ALVTH16601
MIN
SN74ALVTH16601
MIN
UNIT
MAX
MAX
fclock
Clock frequency
150
150
MHz
tw
Pulse duration
LE high
1.8
1.8
ns
CLK high or low
2.3
2.3
A or B before CLK
↑
Data high
4
4
Data low
5.2
5.2
tsu
Setup time
A or B before LE
↓
CLK high
0.7
0.7
ns
CLK low
0.9
0.9
CLKEN before CLK
↑
Data high
1.7
1.7
Data low
2.3
2.3
A or B after CLK
↑
Data high
0.5
0.5
Data low
0.5
0.5
th
Hold time
A or B after LE
↓
CLK high
2.3
2.3
ns
CLK low
2.4
2.4
CLKEN after CLK
↑
Data high
Data low
0.5
0.5
0.5
0.5
timing requirements over recommended operating free-air temperature range, V
CC
= 3.3 V
±
0.3 V
(unless otherwise noted) (see Figure 2)
SN54ALVTH16601
MIN
SN74ALVTH16601
MIN
UNIT
MAX
MAX
fclock
Clock frequency
150
150
MHz
tw
Pulse duration
LE high
1.8
1.8
ns
CLK high or low
2.3
2.3
A or B before CLK
↑
Data high
2.4
2.4
Data low
3.8
3.8
tsu
Setup time
A or B before LE
↓
CLK high
1
1
ns
CLK low
0.6
0.6
CLKEN before CLK
↑
Data high
1.4
1.4
Data low
1.9
1.9
A or B after CLK
↑
Data high
0.5
0.5
Data low
0.5
0.5
th
Hold time
A or B after LE
↓
CLK high
2
2
ns
CLK low
2.3
2.3
CLKEN after CLK
↑
Data high
Data low
0.6
0.5
0.6
0.5
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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