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參數(shù)資料
| 型號： | SN54ALVTH16601WD |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS |
| 中文描述： | 2.5-V/3.3-V 18位通用總線收發(fā)器和三態(tài)輸出 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 196K |
| 代理商： | SN54ALVTH16601WD |
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JULY 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
UBT
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
State-of-the-Art Advanced BiCMOS
Technology (ABT) Widebus
Design for
2.5-V and 3.3-V Operation and Low
Static-Power Dissipation
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 2.3-V to
3.6-V V
CC
)
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
High-Drive (–24/24 mA at 2.5-V and
–32/64 mA at 3.3-V V
CC
)
I
off
and Power-Up 3-State Support Hot
Insertion
Use Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating
Auto3-State Eliminates Bus Current
Loading When Output Exceeds V
CC
+ 0.5 V
Flow-Through Architecture Facilitates
Printed Circuit Board Layout
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
NOTE: For tape and reel order entry:
The DGGR package is abbreviated to GR and
the DGVR package is abbreviated to VR.
description
The ’ALVTH16601 devices are 18-bit universal bus transceivers designed for 2.5-V or 3.3-V V
CC
operation, but
with the capability to provide a TTL interface to a 5-V system environment.
The devices combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked
modes.
Copyright
1999, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UBT and Widebus are trademarks of Texas Instruments Incorporated.
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OEAB
LEAB
A1
GND
A2
A3
V
CC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
V
CC
A16
A17
GND
A18
OEBA
LEBA
CLKENAB
CLKAB
B1
GND
B2
B3
V
CC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V
CC
B16
B17
GND
B18
CLKBA
CLKENBA
SN54ALVTH16601 . . . WD PACKAGE
SN74ALVTH16601 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN74ALVTH16601DGG | 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS |
| SN74ALVTH16601DGV | 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS |
| SN54ALVTH16646 | 2.5-V/3.3-V 16-Bit Bus Transceivers With 3-State Outputs( 2.5V/3.3V 16位總線收發(fā)器(三態(tài)輸出)) |
| SN74ALVTH16646 | 2.5-V/3.3-V 16-Bit Bus Transceivers With 3-State Outputs( 2.5V/3.3V16位總線收發(fā)器(三態(tài)輸出)) |
| SN54ALVTH16821WD | 2.5-V/3.3-V 20-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS |
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