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參數(shù)資料
| 型號： | SN54ALVTH16646 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 2.5-V/3.3-V 16-Bit Bus Transceivers With 3-State Outputs( 2.5V/3.3V 16位總線收發(fā)器(三態(tài)輸出)) |
| 中文描述： | 2.5-V/3.3-V 16位總線收發(fā)器三態(tài)輸出（2.5V/3.3V的16位總線收發(fā)器（三態(tài)輸出）） |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 276K |
| 代理商： | SN54ALVTH16646 |
SN54ALVTH16646, SN74ALVTH16646
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES072A – JUNE 1996 – REVISED JULY 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Members of the Texas Instruments
Widebus
Family
High-Impedance State During Power Up
and Power Down
5-V I/O Compatible
High-Drive Outputs (–32 mA/64 mA)
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
Auto 3-State Eliminates Bus Current
Loading When Voltage at the Output
Exceeds V
CC
Bus-Hold Data Inputs Eliminate the Need
for External Pullup/Pulldown Resistors
Power Off Disables Inputs/Outputs,
Permitting Live Insertion
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
description
The ’ALVTH16646 are 16-bit bus transceivers
designed for 2.5-V or 3.3-V V
CC
operation, but
with the capability to provide a TTL interface to a
5-V system environment.
These devices can be used as two 8-bit
transceivers or one 16-bit transceiver. Data on the
A or B bus is clocked into the registers on the
low-to-high transition of the appropriate clock
(CLKAB or CLKBA) input. Figure 1 illustrates the
four fundamental bus-management functions that
can be performed with the
′
ALVTH16646.
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port may be stored in either register or in both. The
select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry
used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition
between stored and real-time data. DIR determines which bus receives data when OE is low. In the isolation
mode (OE high), A data can be stored in one register and/or B data can be stored in the other register.
When an output function is disabled, the input function is still enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
Copyright
1996, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
SN54ALVTH16646 . . . WD PACKAGE
SN74ALVTH16646 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
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1DIR
1CLKAB
1SAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2SAB
2CLKAB
2DIR
1OE
1CLKBA
1SBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2SBA
2CLKBA
2OE
P
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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| SN74ALVTH16646 | 2.5-V/3.3-V 16-Bit Bus Transceivers With 3-State Outputs( 2.5V/3.3V16位總線收發(fā)器(三態(tài)輸出)) |
| SN54ALVTH16821WD | 2.5-V/3.3-V 20-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS |
| SN74ALVTH16821DGG | 2.5-V/3.3-V 20-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS |
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| SN54ALVTH16821 | 2.5-V/3.3-V 20-Bit Bus-Interface Flip-Flops(2.5V/3.3V 20位總線接口觸發(fā)器(三態(tài)輸出)) |
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